^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Dallas DS1216 RTC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2007 Thomas Bogendoerfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct ds1216_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u8 tsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u8 sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u8 min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u8 hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u8 wday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u8 mday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u8 month;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u8 year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DS1216_HOUR_1224 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DS1216_HOUR_AMPM (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct ds1216_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const u8 magic[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Read the 64 bit we'd like to have - It a series
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * of 64 bits showing up in the LSB of the base register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void ds1216_read(u8 __iomem *ioaddr, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned char c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) c = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) for (j = 0; j < 8; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) c |= (readb(ioaddr) & 0x1) << j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) buf[i] = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void ds1216_write(u8 __iomem *ioaddr, const u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned char c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) c = buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) for (j = 0; j < 8; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) writeb(c, ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) c = c >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static void ds1216_switch_ds_to_clock(u8 __iomem *ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Reset magic pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) readb(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Write 64 bit magic to DS1216 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ds1216_write(ioaddr, magic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int ds1216_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct ds1216_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct ds1216_regs regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ds1216_switch_ds_to_clock(priv->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ds1216_read(priv->ioaddr, (u8 *)®s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) tm->tm_sec = bcd2bin(regs.sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) tm->tm_min = bcd2bin(regs.min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (regs.hour & DS1216_HOUR_1224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* AM/PM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) tm->tm_hour = bcd2bin(regs.hour & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (regs.hour & DS1216_HOUR_AMPM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) tm->tm_hour += 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) tm->tm_hour = bcd2bin(regs.hour & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) tm->tm_wday = (regs.wday & 7) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) tm->tm_mday = bcd2bin(regs.mday & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) tm->tm_mon = bcd2bin(regs.month & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) tm->tm_year = bcd2bin(regs.year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (tm->tm_year < 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) tm->tm_year += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int ds1216_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct ds1216_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct ds1216_regs regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ds1216_switch_ds_to_clock(priv->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ds1216_read(priv->ioaddr, (u8 *)®s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) regs.tsec = 0; /* clear 0.1 and 0.01 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) regs.sec = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) regs.min = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) regs.hour &= DS1216_HOUR_1224;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (regs.hour && tm->tm_hour > 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) regs.hour |= DS1216_HOUR_AMPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) tm->tm_hour -= 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) regs.hour |= bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regs.wday &= ~7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) regs.wday |= tm->tm_wday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) regs.mday = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) regs.month = bin2bcd(tm->tm_mon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) regs.year = bin2bcd(tm->tm_year % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ds1216_switch_ds_to_clock(priv->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ds1216_write(priv->ioaddr, (u8 *)®s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct rtc_class_ops ds1216_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .read_time = ds1216_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .set_time = ds1216_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int __init ds1216_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct ds1216_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 dummy[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) priv->ioaddr = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (IS_ERR(priv->ioaddr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return PTR_ERR(priv->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) priv->rtc = devm_rtc_device_register(&pdev->dev, "ds1216",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) &ds1216_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (IS_ERR(priv->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return PTR_ERR(priv->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* dummy read to get clock into a known state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ds1216_read(priv->ioaddr, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct platform_driver ds1216_rtc_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "rtc-ds1216",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) module_platform_driver_probe(ds1216_rtc_platform_driver, ds1216_rtc_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MODULE_AUTHOR("Thomas Bogendoerfer <tsbogend@alpha.franken.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MODULE_DESCRIPTION("DS1216 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MODULE_ALIAS("platform:rtc-ds1216");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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