^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DaVinci Power Management and Real Time Clock Driver for TI platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Texas Instruments, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * The DaVinci RTC is a simple RTC with the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Sec: 0 - 59 : BCD count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Min: 0 - 59 : BCD count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Hour: 0 - 23 : BCD count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* PRTC interface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DAVINCI_PRTCIF_PID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PRTCIF_CTLR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PRTCIF_LDATA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PRTCIF_UDATA 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PRTCIF_INTEN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PRTCIF_INTFLG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* PRTCIF_CTLR bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PRTCIF_CTLR_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PRTCIF_CTLR_SIZE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PRTCIF_CTLR_DIR BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PRTCIF_CTLR_BENU_MSB BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PRTCIF_CTLR_BENU_3RD_BYTE BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PRTCIF_CTLR_BENU_2ND_BYTE BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PRTCIF_CTLR_BENU_LSB BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PRTCIF_CTLR_BENU_MASK (0x00F00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PRTCIF_CTLR_BENL_MSB BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PRTCIF_CTLR_BENL_3RD_BYTE BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PRTCIF_CTLR_BENL_2ND_BYTE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PRTCIF_CTLR_BENL_LSB BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PRTCIF_CTLR_BENL_MASK (0x000F0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* PRTCIF_INTEN bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PRTCIF_INTEN_RTCSS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PRTCIF_INTEN_RTCIF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PRTCIF_INTEN_MASK (PRTCIF_INTEN_RTCSS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) | PRTCIF_INTEN_RTCIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* PRTCIF_INTFLG bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PRTCIF_INTFLG_RTCSS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PRTCIF_INTFLG_RTCIF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PRTCIF_INTFLG_MASK (PRTCIF_INTFLG_RTCSS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) | PRTCIF_INTFLG_RTCIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* PRTC subsystem registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PRTCSS_RTC_INTC_EXTENA1 (0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PRTCSS_RTC_CTRL (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PRTCSS_RTC_WDT (0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PRTCSS_RTC_TMR0 (0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PRTCSS_RTC_TMR1 (0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PRTCSS_RTC_CCTRL (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PRTCSS_RTC_SEC (0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PRTCSS_RTC_MIN (0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PRTCSS_RTC_HOUR (0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PRTCSS_RTC_DAY0 (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PRTCSS_RTC_DAY1 (0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PRTCSS_RTC_AMIN (0x1A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PRTCSS_RTC_AHOUR (0x1B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PRTCSS_RTC_ADAY0 (0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PRTCSS_RTC_ADAY1 (0x1D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PRTCSS_RTC_CLKC_CNT (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* PRTCSS_RTC_INTC_EXTENA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PRTCSS_RTC_INTC_EXTENA1_MASK (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* PRTCSS_RTC_CTRL bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PRTCSS_RTC_CTRL_WDTBUS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PRTCSS_RTC_CTRL_WEN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PRTCSS_RTC_CTRL_WDRT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PRTCSS_RTC_CTRL_WDTFLG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PRTCSS_RTC_CTRL_TE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PRTCSS_RTC_CTRL_TIEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PRTCSS_RTC_CTRL_TMRFLG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PRTCSS_RTC_CTRL_TMMD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* PRTCSS_RTC_CCTRL bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PRTCSS_RTC_CCTRL_CALBUSY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PRTCSS_RTC_CCTRL_DAEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PRTCSS_RTC_CCTRL_HAEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PRTCSS_RTC_CCTRL_MAEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PRTCSS_RTC_CCTRL_ALMFLG BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PRTCSS_RTC_CCTRL_AIEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PRTCSS_RTC_CCTRL_CAEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static DEFINE_SPINLOCK(davinci_rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct davinci_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 val, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel(val, davinci_rtc->base + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return readl(davinci_rtc->base + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned long val, u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) rtcif_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) rtcif_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) rtcif_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PRTCIF_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) rtcif_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return rtcif_read(davinci_rtc, PRTCIF_LDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PRTCSS_RTC_CCTRL_CALBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct davinci_rtc *davinci_rtc = class_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 irq_flg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 alm_irq, tmr_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 rtc_ctrl, rtc_cctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PRTCIF_INTFLG_RTCSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PRTCSS_RTC_CCTRL_ALMFLG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PRTCSS_RTC_CTRL_TMRFLG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (irq_flg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (alm_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) events |= RTC_IRQF | RTC_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) rtc_cctrl |= PRTCSS_RTC_CCTRL_ALMFLG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) } else if (tmr_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) events |= RTC_IRQF | RTC_PF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) rtc_ctrl |= PRTCSS_RTC_CTRL_TMRFLG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PRTCIF_INTFLG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) rtc_update_irq(davinci_rtc->rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 rtc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) spin_lock_irqsave(&davinci_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case RTC_WIE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case RTC_WIE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) spin_unlock_irqrestore(&davinci_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void convertfromdays(u16 days, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int tmp_days, year, mon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) for (year = 2000;; year++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) tmp_days = rtc_year_days(1, 12, year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (days >= tmp_days)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) days -= tmp_days;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) for (mon = 0;; mon++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) tmp_days = rtc_month_days(mon, year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (days >= tmp_days) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) days -= tmp_days;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) tm->tm_year = year - 1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) tm->tm_mon = mon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) tm->tm_mday = days + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static void convert2days(u16 *days, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) *days = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) for (i = 2000; i < 1900 + tm->tm_year; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *days += rtc_year_days(1, 12, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u16 days = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u8 day0, day1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) spin_lock_irqsave(&davinci_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) spin_unlock_irqrestore(&davinci_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) days |= day1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) days <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) days |= day0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) convertfromdays(days, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u16 days;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 rtc_cctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) convert2days(&days, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) spin_lock_irqsave(&davinci_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) spin_unlock_irqrestore(&davinci_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int davinci_rtc_alarm_irq_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) spin_lock_irqsave(&davinci_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PRTCSS_RTC_CCTRL_HAEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PRTCSS_RTC_CCTRL_MAEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PRTCSS_RTC_CCTRL_ALMFLG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PRTCSS_RTC_CCTRL_AIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) spin_unlock_irqrestore(&davinci_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u16 days = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u8 day0, day1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) alm->time.tm_sec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) spin_lock_irqsave(&davinci_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) spin_unlock_irqrestore(&davinci_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) days |= day1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) days <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) days |= day0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) convertfromdays(days, &alm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) alm->pending = !!(rtcss_read(davinci_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PRTCSS_RTC_CCTRL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PRTCSS_RTC_CCTRL_AIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) alm->enabled = alm->pending && device_may_wakeup(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u16 days;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) convert2days(&days, &alm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) spin_lock_irqsave(&davinci_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) davinci_rtcss_calendar_wait(davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) spin_unlock_irqrestore(&davinci_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const struct rtc_class_ops davinci_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .ioctl = davinci_rtc_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .read_time = davinci_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .set_time = davinci_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .alarm_irq_enable = davinci_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .read_alarm = davinci_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .set_alarm = davinci_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int __init davinci_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct davinci_rtc *davinci_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) davinci_rtc = devm_kzalloc(&pdev->dev, sizeof(struct davinci_rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (!davinci_rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) davinci_rtc->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (davinci_rtc->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return davinci_rtc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) davinci_rtc->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (IS_ERR(davinci_rtc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return PTR_ERR(davinci_rtc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) platform_set_drvdata(pdev, davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) davinci_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (IS_ERR(davinci_rtc->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return PTR_ERR(davinci_rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) davinci_rtc->rtc->ops = &davinci_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) davinci_rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) davinci_rtc->rtc->range_max = RTC_TIMESTAMP_BEGIN_2000 + (1 << 16) * 86400ULL - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = devm_request_irq(dev, davinci_rtc->irq, davinci_rtc_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 0, "davinci_rtc", davinci_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_err(dev, "unable to register davinci RTC interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PRTCSS_RTC_INTC_EXTENA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) device_init_wakeup(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return rtc_register_device(davinci_rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int __exit davinci_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) device_init_wakeup(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static struct platform_driver davinci_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .remove = __exit_p(davinci_rtc_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .name = "rtc_davinci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) module_platform_driver_probe(davinci_rtc_driver, davinci_rtc_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar@ridgerun.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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