^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Motorola CPCAP PMIC RTC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on cpcap-regulator.c from Motorola Linux kernel tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009 Motorola, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Rewritten for mainline kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * - use DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * - use regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * - use standard interrupt framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * - use managed device resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * - remove custom "secure clock daemon" helpers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright (C) 2017 Sebastian Reichel <sre@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mfd/motorola-cpcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SECS_PER_DAY 86400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DAY_MASK 0x7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TOD1_MASK 0x00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TOD2_MASK 0x01FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct cpcap_time {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int day;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int tod1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int tod2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct cpcap_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct rtc_device *rtc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u16 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int alarm_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) bool alarm_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int update_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) bool update_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void cpcap2rtc_time(struct rtc_time *rtc, struct cpcap_time *cpcap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned long int tod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long int time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) tod = (cpcap->tod1 & TOD1_MASK) | ((cpcap->tod2 & TOD2_MASK) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) time = tod + ((cpcap->day & DAY_MASK) * SECS_PER_DAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) rtc_time64_to_tm(time, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void rtc2cpcap_time(struct cpcap_time *cpcap, struct rtc_time *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) time = rtc_tm_to_time64(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) cpcap->day = time / SECS_PER_DAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) time %= SECS_PER_DAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) cpcap->tod2 = (time >> 8) & TOD2_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) cpcap->tod1 = time & TOD1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int cpcap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct cpcap_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (rtc->alarm_enabled == enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) enable_irq(rtc->alarm_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) disable_irq(rtc->alarm_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) rtc->alarm_enabled = !!enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int cpcap_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct cpcap_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct cpcap_time cpcap_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int temp_tod2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = regmap_read(rtc->regmap, CPCAP_REG_TOD2, &temp_tod2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ret |= regmap_read(rtc->regmap, CPCAP_REG_DAY, &cpcap_tm.day);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ret |= regmap_read(rtc->regmap, CPCAP_REG_TOD1, &cpcap_tm.tod1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret |= regmap_read(rtc->regmap, CPCAP_REG_TOD2, &cpcap_tm.tod2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (temp_tod2 > cpcap_tm.tod2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret |= regmap_read(rtc->regmap, CPCAP_REG_DAY, &cpcap_tm.day);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_err(dev, "Failed to read time\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) cpcap2rtc_time(tm, &cpcap_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int cpcap_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct cpcap_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct cpcap_time cpcap_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) rtc2cpcap_time(&cpcap_tm, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (rtc->alarm_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) disable_irq(rtc->alarm_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (rtc->update_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) disable_irq(rtc->update_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (rtc->vendor == CPCAP_VENDOR_ST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* The TOD1 and TOD2 registers MUST be written in this order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * for the change to properly set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TOD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) TOD1_MASK, cpcap_tm.tod1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TOD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) TOD2_MASK, cpcap_tm.tod2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_DAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DAY_MASK, cpcap_tm.day);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Clearing the upper lower 8 bits of the TOD guarantees that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * the upper half of TOD (TOD2) will not increment for 0xFF RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * ticks (255 seconds). During this time we can safely write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * to DAY, TOD2, then TOD1 (in that order) and expect RTC to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * synchronized to the exact time requested upon the final write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * to TOD1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TOD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) TOD1_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_DAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DAY_MASK, cpcap_tm.day);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TOD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) TOD2_MASK, cpcap_tm.tod2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TOD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) TOD1_MASK, cpcap_tm.tod1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (rtc->update_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) enable_irq(rtc->update_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (rtc->alarm_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) enable_irq(rtc->alarm_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int cpcap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct cpcap_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct cpcap_time cpcap_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) alrm->enabled = rtc->alarm_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ret = regmap_read(rtc->regmap, CPCAP_REG_DAYA, &cpcap_tm.day);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret |= regmap_read(rtc->regmap, CPCAP_REG_TODA2, &cpcap_tm.tod2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret |= regmap_read(rtc->regmap, CPCAP_REG_TODA1, &cpcap_tm.tod1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dev_err(dev, "Failed to read time\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) cpcap2rtc_time(&alrm->time, &cpcap_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return rtc_valid_tm(&alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int cpcap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct cpcap_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct cpcap_time cpcap_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) rtc2cpcap_time(&cpcap_tm, &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (rtc->alarm_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) disable_irq(rtc->alarm_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = regmap_update_bits(rtc->regmap, CPCAP_REG_DAYA, DAY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) cpcap_tm.day);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TODA2, TOD2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) cpcap_tm.tod2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TODA1, TOD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) cpcap_tm.tod1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) enable_irq(rtc->alarm_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) rtc->alarm_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct rtc_class_ops cpcap_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .read_time = cpcap_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .set_time = cpcap_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .read_alarm = cpcap_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .set_alarm = cpcap_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .alarm_irq_enable = cpcap_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static irqreturn_t cpcap_rtc_alarm_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct cpcap_rtc *rtc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static irqreturn_t cpcap_rtc_update_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct cpcap_rtc *rtc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int cpcap_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct cpcap_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) rtc->regmap = dev_get_regmap(dev->parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (!rtc->regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) rtc->rtc_dev = devm_rtc_allocate_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (IS_ERR(rtc->rtc_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return PTR_ERR(rtc->rtc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) rtc->rtc_dev->ops = &cpcap_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) rtc->rtc_dev->range_max = (timeu64_t) (DAY_MASK + 1) * SECS_PER_DAY - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) err = cpcap_get_vendor(dev, rtc->regmap, &rtc->vendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) rtc->alarm_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) err = devm_request_threaded_irq(dev, rtc->alarm_irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) cpcap_rtc_alarm_irq, IRQF_TRIGGER_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "rtc_alarm", rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_err(dev, "Could not request alarm irq: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) disable_irq(rtc->alarm_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Stock Android uses the 1 Hz interrupt for "secure clock daemon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * which is not supported by the mainline kernel. The mainline kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * does not use the irq at the moment, but we explicitly request and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * disable it, so that its masked and does not wake up the processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * every second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) rtc->update_irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) err = devm_request_threaded_irq(dev, rtc->update_irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) cpcap_rtc_update_irq, IRQF_TRIGGER_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "rtc_1hz", rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dev_err(dev, "Could not request update irq: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) disable_irq(rtc->update_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) err = device_init_wakeup(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_err(dev, "wakeup initialization failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* ignore error and continue without wakeup support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return rtc_register_device(rtc->rtc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const struct of_device_id cpcap_rtc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { .compatible = "motorola,cpcap-rtc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MODULE_DEVICE_TABLE(of, cpcap_rtc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static struct platform_driver cpcap_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .probe = cpcap_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .name = "cpcap-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .of_match_table = cpcap_rtc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) module_platform_driver(cpcap_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) MODULE_ALIAS("platform:cpcap-rtc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MODULE_DESCRIPTION("CPCAP RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MODULE_AUTHOR("Sebastian Reichel <sre@kernel.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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