^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2007-2009 ST-Ericsson AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Real Time Clock interface for ST-Ericsson AB COH 901 331 RTC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Linus Walleij <linus.walleij@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on rtc-pl031.c by Deepak Saxena <dsaxena@plexity.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2006 (c) MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Registers in the COH 901 331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Alarm value 32bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define COH901331_ALARM 0x00U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Used to set current time 32bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define COH901331_SET_TIME 0x04U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Indication if current time is valid 32bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define COH901331_VALID 0x08U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Read the current time 32bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define COH901331_CUR_TIME 0x0cU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Event register for the "alarm" interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define COH901331_IRQ_EVENT 0x10U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Mask register for the "alarm" interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define COH901331_IRQ_MASK 0x14U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Force register for the "alarm" interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define COH901331_IRQ_FORCE 0x18U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Reference to RTC block clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Notice that the frequent clk_enable()/clk_disable() on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * clock is mainly to be able to turn on/off other clocks in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * hierarchy as needed, the RTC clock is always on anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct coh901331_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) void __iomem *virtbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 irqmaskstore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static irqreturn_t coh901331_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct coh901331_port *rtap = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) clk_enable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Ack IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) writel(1, rtap->virtbase + COH901331_IRQ_EVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Disable the interrupt. This is necessary because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * the RTC lives on a lower-clocked line and will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * not release the IRQ line until after a few (slower)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * clock cycles. The interrupt will be re-enabled when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * a new alarm is set anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel(0, rtap->virtbase + COH901331_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) clk_disable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Set alarm flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) rtc_update_irq(rtap->rtc, 1, RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int coh901331_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct coh901331_port *rtap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clk_enable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Check if the time is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!readl(rtap->virtbase + COH901331_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) clk_disable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) rtc_time64_to_tm(readl(rtap->virtbase + COH901331_CUR_TIME), tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) clk_disable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int coh901331_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct coh901331_port *rtap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) clk_enable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writel(rtc_tm_to_time64(tm), rtap->virtbase + COH901331_SET_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clk_disable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int coh901331_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct coh901331_port *rtap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) clk_enable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) rtc_time64_to_tm(readl(rtap->virtbase + COH901331_ALARM), &alarm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) alarm->pending = readl(rtap->virtbase + COH901331_IRQ_EVENT) & 1U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) alarm->enabled = readl(rtap->virtbase + COH901331_IRQ_MASK) & 1U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clk_disable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int coh901331_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct coh901331_port *rtap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long time = rtc_tm_to_time64(&alarm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) clk_enable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel(time, rtap->virtbase + COH901331_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) writel(alarm->enabled, rtap->virtbase + COH901331_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) clk_disable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int coh901331_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct coh901331_port *rtap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) clk_enable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writel(1, rtap->virtbase + COH901331_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) writel(0, rtap->virtbase + COH901331_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) clk_disable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct rtc_class_ops coh901331_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .read_time = coh901331_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .set_time = coh901331_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .read_alarm = coh901331_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .set_alarm = coh901331_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .alarm_irq_enable = coh901331_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int __exit coh901331_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct coh901331_port *rtap = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (rtap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) clk_unprepare(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int __init coh901331_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct coh901331_port *rtap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) rtap = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) sizeof(struct coh901331_port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (!rtap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) rtap->virtbase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (IS_ERR(rtap->virtbase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return PTR_ERR(rtap->virtbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) rtap->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (devm_request_irq(&pdev->dev, rtap->irq, coh901331_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "RTC COH 901 331 Alarm", rtap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) rtap->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (IS_ERR(rtap->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = PTR_ERR(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev_err(&pdev->dev, "could not get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) rtap->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (IS_ERR(rtap->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return PTR_ERR(rtap->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) rtap->rtc->ops = &coh901331_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rtap->rtc->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* We enable/disable the clock only to assure it works */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = clk_prepare_enable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_err(&pdev->dev, "could not enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) clk_disable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) platform_set_drvdata(pdev, rtap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ret = rtc_register_device(rtap->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) goto out_no_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) out_no_rtc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) clk_unprepare(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int coh901331_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct coh901331_port *rtap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * If this RTC alarm will be used for waking the system up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * don't disable it of course. Else we just disable the alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * and await suspension.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (device_may_wakeup(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) enable_irq_wake(rtap->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) clk_enable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) rtap->irqmaskstore = readl(rtap->virtbase + COH901331_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) writel(0, rtap->virtbase + COH901331_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) clk_disable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) clk_unprepare(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int coh901331_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct coh901331_port *rtap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = clk_prepare(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (device_may_wakeup(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) disable_irq_wake(rtap->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) clk_enable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) writel(rtap->irqmaskstore, rtap->virtbase + COH901331_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) clk_disable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static SIMPLE_DEV_PM_OPS(coh901331_pm_ops, coh901331_suspend, coh901331_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void coh901331_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct coh901331_port *rtap = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) clk_enable(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) writel(0, rtap->virtbase + COH901331_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) clk_disable_unprepare(rtap->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct of_device_id coh901331_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { .compatible = "stericsson,coh901331" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MODULE_DEVICE_TABLE(of, coh901331_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static struct platform_driver coh901331_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .name = "rtc-coh901331",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .pm = &coh901331_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .of_match_table = coh901331_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .remove = __exit_p(coh901331_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .shutdown = coh901331_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) module_platform_driver_probe(coh901331_driver, coh901331_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_DESCRIPTION("ST-Ericsson AB COH 901 331 RTC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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