^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Au1xxx counter0 (aka Time-Of-Year counter) RTC interface driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* All current Au1xxx SoCs have 2 counters fed by an external 32.768 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * crystal. Counter 0, which keeps counting during sleep/powerdown, is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * used to count seconds since the beginning of the unix epoch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * The counters must be configured and enabled by bootloader/board code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * no checks as to whether they really get a proper 32.768kHz clock are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * made as this would take far too long.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* 32kHz clock enabled and detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int au1xtoy_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) t = alchemy_rdsys(AU1000_SYS_TOYREAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) rtc_time64_to_tm(t, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int au1xtoy_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) t = rtc_tm_to_time64(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) alchemy_wrsys(t, AU1000_SYS_TOYWRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* wait for the pending register write to succeed. This can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * take up to 6 seconds...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C0S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct rtc_class_ops au1xtoy_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .read_time = au1xtoy_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .set_time = au1xtoy_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int au1xtoy_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct rtc_device *rtcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) t = alchemy_rdsys(AU1000_SYS_CNTRCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (!(t & CNTR_OK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dev_err(&pdev->dev, "counters not working; aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* set counter0 tickrate to 1Hz if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (alchemy_rdsys(AU1000_SYS_TOYTRIM) != 32767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* wait until hardware gives access to TRIM register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) t = 0x00100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T0S) && --t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (!t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* timed out waiting for register access; assume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * counters are unusable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dev_err(&pdev->dev, "timeout waiting for access\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* set 1Hz TOY tick rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) alchemy_wrsys(32767, AU1000_SYS_TOYTRIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* wait until the hardware allows writes to the counter reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C0S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) rtcdev = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (IS_ERR(rtcdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return PTR_ERR(rtcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) rtcdev->ops = &au1xtoy_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) rtcdev->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) platform_set_drvdata(pdev, rtcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return rtc_register_device(rtcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct platform_driver au1xrtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .name = "rtc-au1xxx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) module_platform_driver_probe(au1xrtc_driver, au1xtoy_rtc_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MODULE_DESCRIPTION("Au1xxx TOY-counter-based RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MODULE_AUTHOR("Manuel Lauss <manuel.lauss@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MODULE_ALIAS("platform:rtc-au1xxx");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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