^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * "RTT as Real Time Clock" driver for AT91SAM9 SoC family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) 2007 Michel Benoit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on rtc-at91rm9200.c by Rick Bronson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * This driver uses two configurable hardware resources that live in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * AT91SAM9 backup power domain (intended to be powered at all times)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * to implement the Real Time Clock interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * - A "Real-time Timer" (RTT) counts up in seconds from a base time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * We can't assign the counter value (CRTV) ... but we can reset it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * - One of the "General Purpose Backup Registers" (GPBRs) holds the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * base time, normally an offset from the beginning of the POSIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * epoch (1970-Jan-1 00:00:00 UTC). Some systems also include the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * local timezone's offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * The RTC's value is the RTT counter plus that offset. The RTC's alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * is likewise a base (ALMV) plus that offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Not all RTTs will be used as RTCs; some systems have multiple RTTs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * choose from, or a "real" RTC module. All systems have multiple GPBR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * registers available, likewise usable for more than "RTC" support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AT91_RTT_MR 0x00 /* Real-time Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AT91_RTT_RTPRES (0xffff << 0) /* Timer Prescaler Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AT91_RTT_ALMIEN BIT(16) /* Alarm Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AT91_RTT_RTTINCIEN BIT(17) /* Increment Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AT91_RTT_RTTRST BIT(18) /* Timer Restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AT91_RTT_AR 0x04 /* Real-time Alarm Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AT91_RTT_VR 0x08 /* Real-time Value Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AT91_RTT_SR 0x0c /* Real-time Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AT91_RTT_ALMS BIT(0) /* Alarm Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AT91_RTT_RTTINC BIT(1) /* Timer Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * We store ALARM_DISABLED in ALMV to record that no alarm is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * It's also the reset value for that field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ALARM_DISABLED ((u32)~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct sam9_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void __iomem *rtt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct rtc_device *rtcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct regmap *gpbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int gpbr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct clk *sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) bool suspended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define rtt_readl(rtc, field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) readl((rtc)->rtt + AT91_RTT_ ## field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define rtt_writel(rtc, field, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) writel((val), (rtc)->rtt + AT91_RTT_ ## field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline unsigned int gpbr_readl(struct sam9_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) regmap_read(rtc->gpbr, rtc->gpbr_offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static inline void gpbr_writel(struct sam9_rtc *rtc, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) regmap_write(rtc->gpbr, rtc->gpbr_offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Read current time and date in RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct sam9_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 secs, secs2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* read current time offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) offset = gpbr_readl(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (offset == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* reread the counter to help sync the two clock domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) secs = rtt_readl(rtc, VR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) secs2 = rtt_readl(rtc, VR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (secs != secs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) secs = rtt_readl(rtc, VR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) rtc_time64_to_tm(offset + secs, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dev_dbg(dev, "%s: %ptR\n", __func__, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Set current time and date in RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct sam9_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 offset, alarm, mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dev_dbg(dev, "%s: %ptR\n", __func__, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) secs = rtc_tm_to_time64(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) mr = rtt_readl(rtc, MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* read current time offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) offset = gpbr_readl(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* store the new base time in a battery backup register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) secs += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) gpbr_writel(rtc, secs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* adjust the alarm time for the new base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) alarm = rtt_readl(rtc, AR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (alarm != ALARM_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (offset > secs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* time jumped backwards, increase time until alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) alarm += (offset - secs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } else if ((alarm + offset) > secs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* time jumped forwards, decrease time until alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) alarm -= (secs - offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* time jumped past the alarm, disable alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) alarm = ALARM_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mr &= ~AT91_RTT_ALMIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) rtt_writel(rtc, AR, alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* reset the timer, and re-enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) rtt_writel(rtc, MR, mr | AT91_RTT_RTTRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct sam9_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct rtc_time *tm = &alrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 alarm = rtt_readl(rtc, AR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) offset = gpbr_readl(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (offset == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) memset(alrm, 0, sizeof(*alrm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (alarm != ALARM_DISABLED && offset != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) rtc_time64_to_tm(offset + alarm, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_dbg(dev, "%s: %ptR\n", __func__, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (rtt_readl(rtc, MR) & AT91_RTT_ALMIEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) alrm->enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct sam9_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct rtc_time *tm = &alrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned long secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) secs = rtc_tm_to_time64(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) offset = gpbr_readl(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (offset == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* time is not set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mr = rtt_readl(rtc, MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* alarm in the past? finish and leave disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (secs <= offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) rtt_writel(rtc, AR, ALARM_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* else set alarm and maybe enable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) rtt_writel(rtc, AR, secs - offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (alrm->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_dbg(dev, "%s: %ptR\n", __func__, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct sam9_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 mr = rtt_readl(rtc, MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_dbg(dev, "alarm_irq_enable: enabled=%08x, mr %08x\n", enabled, mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * Provide additional RTC information in /proc/driver/rtc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct sam9_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 mr = rtt_readl(rtc, MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) seq_printf(seq, "update_IRQ\t: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) (mr & AT91_RTT_RTTINCIEN) ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static irqreturn_t at91_rtc_cache_events(struct sam9_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 sr, mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Shared interrupt may be for another device. Note: reading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * SR clears it, so we must only read it in this irq handler!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mr = rtt_readl(rtc, MR) & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) sr = rtt_readl(rtc, SR) & (mr >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (!sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* alarm status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (sr & AT91_RTT_ALMS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rtc->events |= (RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* timer update/increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (sr & AT91_RTT_RTTINC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) rtc->events |= (RTC_UF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static void at91_rtc_flush_events(struct sam9_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (!rtc->events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) rtc_update_irq(rtc->rtcdev, 1, rtc->events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) rtc->events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pr_debug("%s: num=%ld, events=0x%02lx\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) rtc->events >> 8, rtc->events & 0x000000FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * IRQ handler for the RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static irqreturn_t at91_rtc_interrupt(int irq, void *_rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct sam9_rtc *rtc = _rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) spin_lock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = at91_rtc_cache_events(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* We're called in suspended state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (rtc->suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Mask irqs coming from this peripheral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) rtt_writel(rtc, MR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) rtt_readl(rtc, MR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Trigger a system wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pm_system_wakeup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) at91_rtc_flush_events(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) spin_unlock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const struct rtc_class_ops at91_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .read_time = at91_rtc_readtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .set_time = at91_rtc_settime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .read_alarm = at91_rtc_readalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .set_alarm = at91_rtc_setalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .proc = at91_rtc_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .alarm_irq_enable = at91_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * Initialize and install RTC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int at91_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct sam9_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned int sclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct of_phandle_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (!rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) spin_lock_init(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) rtc->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* platform setup code should have handled this; sigh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (!device_can_wakeup(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) rtc->rtt = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (IS_ERR(rtc->rtt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return PTR_ERR(rtc->rtt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "atmel,rtt-rtc-time-reg", 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) &args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) rtc->gpbr = syscon_node_to_regmap(args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) rtc->gpbr_offset = args.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (IS_ERR(rtc->gpbr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev_err(&pdev->dev, "failed to retrieve gpbr regmap, aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) rtc->sclk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (IS_ERR(rtc->sclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return PTR_ERR(rtc->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = clk_prepare_enable(rtc->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_err(&pdev->dev, "Could not enable slow clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) sclk_rate = clk_get_rate(rtc->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!sclk_rate || sclk_rate > AT91_RTT_RTPRES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_err(&pdev->dev, "Invalid slow clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mr = rtt_readl(rtc, MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* unless RTT is counting at 1 Hz, re-initialize it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if ((mr & AT91_RTT_RTPRES) != sclk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) mr = AT91_RTT_RTTRST | (sclk_rate & AT91_RTT_RTPRES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) gpbr_writel(rtc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* disable all interrupts (same as on shutdown path) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) mr &= ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) rtt_writel(rtc, MR, mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) rtc->rtcdev = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (IS_ERR(rtc->rtcdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = PTR_ERR(rtc->rtcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) rtc->rtcdev->ops = &at91_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) rtc->rtcdev->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* register irq handler after we know what name we'll use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = devm_request_irq(&pdev->dev, rtc->irq, at91_rtc_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) IRQF_SHARED | IRQF_COND_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_name(&rtc->rtcdev->dev), rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_dbg(&pdev->dev, "can't share IRQ %d?\n", rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* NOTE: sam9260 rev A silicon has a ROM bug which resets the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * RTT on at least some reboots. If you have that chip, you must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * initialize the time from some external source like a GPS, wall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * clock, discrete RTC, etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (gpbr_readl(rtc) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_warn(&pdev->dev, "%s: SET TIME!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev_name(&rtc->rtcdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return rtc_register_device(rtc->rtcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) clk_disable_unprepare(rtc->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Disable and remove the RTC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int at91_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct sam9_rtc *rtc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u32 mr = rtt_readl(rtc, MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) clk_disable_unprepare(rtc->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static void at91_rtc_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct sam9_rtc *rtc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 mr = rtt_readl(rtc, MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) rtt_writel(rtc, MR, mr & ~rtc->imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* AT91SAM9 RTC Power management control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static int at91_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct sam9_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u32 mr = rtt_readl(rtc, MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * This IRQ is shared with DBGU and other hardware which isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * necessarily a wakeup event source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (rtc->imr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (device_may_wakeup(dev) && (mr & AT91_RTT_ALMIEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) enable_irq_wake(rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) spin_lock_irqsave(&rtc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) rtc->suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) spin_unlock_irqrestore(&rtc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* don't let RTTINC cause wakeups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (mr & AT91_RTT_RTTINCIEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) rtt_writel(rtc, MR, mr & ~rtc->imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int at91_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct sam9_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u32 mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (rtc->imr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) disable_irq_wake(rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) mr = rtt_readl(rtc, MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) rtt_writel(rtc, MR, mr | rtc->imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) spin_lock_irqsave(&rtc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) rtc->suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) at91_rtc_cache_events(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) at91_rtc_flush_events(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) spin_unlock_irqrestore(&rtc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const struct of_device_id at91_rtc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) { .compatible = "atmel,at91sam9260-rtt" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static struct platform_driver at91_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .probe = at91_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .remove = at91_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .shutdown = at91_rtc_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .name = "rtc-at91sam9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .pm = &at91_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .of_match_table = of_match_ptr(at91_rtc_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) module_platform_driver(at91_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MODULE_AUTHOR("Michel Benoit");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MODULE_DESCRIPTION("RTC driver for Atmel AT91SAM9x");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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