^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Real Time Clock interface for Linux on Atmel AT91RM9200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2002 Rick Bronson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Converted to RTC class model by Andrew Victor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Ported to Linux 2.6 by Steven Scholz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Based on s3c2410-rtc.c Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Based on sa1100-rtc.c by Nils Faerber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Based on rtc.c by Paul Gortmaker
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AT91_RTC_CR 0x00 /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AT91_RTC_UPDTIM BIT(0) /* Update Request Time Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AT91_RTC_UPDCAL BIT(1) /* Update Request Calendar Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AT91_RTC_MR 0x04 /* Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AT91_RTC_TIMR 0x08 /* Time Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AT91_RTC_SEC GENMASK(6, 0) /* Current Second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AT91_RTC_MIN GENMASK(14, 8) /* Current Minute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AT91_RTC_HOUR GENMASK(21, 16) /* Current Hour */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AT91_RTC_AMPM BIT(22) /* Ante Meridiem Post Meridiem Indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AT91_RTC_CALR 0x0c /* Calendar Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AT91_RTC_CENT GENMASK(6, 0) /* Current Century */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AT91_RTC_YEAR GENMASK(15, 8) /* Current Year */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AT91_RTC_MONTH GENMASK(20, 16) /* Current Month */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AT91_RTC_DAY GENMASK(23, 21) /* Current Day */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AT91_RTC_DATE GENMASK(29, 24) /* Current Date */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AT91_RTC_TIMALR 0x10 /* Time Alarm Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AT91_RTC_SECEN BIT(7) /* Second Alarm Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AT91_RTC_MINEN BIT(15) /* Minute Alarm Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AT91_RTC_HOUREN BIT(23) /* Hour Alarm Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AT91_RTC_CALALR 0x14 /* Calendar Alarm Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AT91_RTC_MTHEN BIT(23) /* Month Alarm Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AT91_RTC_DATEEN BIT(31) /* Date Alarm Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AT91_RTC_SR 0x18 /* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AT91_RTC_ACKUPD BIT(0) /* Acknowledge for Update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AT91_RTC_ALARM BIT(1) /* Alarm Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AT91_RTC_SECEV BIT(2) /* Second Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AT91_RTC_TIMEV BIT(3) /* Time Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AT91_RTC_CALEV BIT(4) /* Calendar Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AT91_RTC_SCCR 0x1c /* Status Clear Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AT91_RTC_IER 0x20 /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AT91_RTC_IMR 0x28 /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AT91_RTC_VER 0x2c /* Valid Entry Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AT91_RTC_NVTIM BIT(0) /* Non valid Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AT91_RTC_NVCAL BIT(1) /* Non valid Calendar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AT91_RTC_NVTIMALR BIT(2) /* Non valid Time Alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AT91_RTC_NVCALALR BIT(3) /* Non valid Calendar Alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define at91_rtc_read(field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) readl_relaxed(at91_rtc_regs + field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define at91_rtc_write(field, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writel_relaxed((val), at91_rtc_regs + field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct at91_rtc_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) bool use_shadow_imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct at91_rtc_config *at91_rtc_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static DECLARE_COMPLETION(at91_rtc_updated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static DECLARE_COMPLETION(at91_rtc_upd_rdy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void __iomem *at91_rtc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static DEFINE_SPINLOCK(at91_rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static u32 at91_rtc_shadow_imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static bool suspended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static DEFINE_SPINLOCK(suspended_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static unsigned long cached_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static u32 at91_rtc_imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct clk *sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void at91_rtc_write_ier(u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) spin_lock_irqsave(&at91_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) at91_rtc_shadow_imr |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) at91_rtc_write(AT91_RTC_IER, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) spin_unlock_irqrestore(&at91_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void at91_rtc_write_idr(u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) spin_lock_irqsave(&at91_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) at91_rtc_write(AT91_RTC_IDR, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Register read back (of any RTC-register) needed to make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * IDR-register write has reached the peripheral before updating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * shadow mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Note that there is still a possibility that the mask is updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * before interrupts have actually been disabled in hardware. The only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * way to be certain would be to poll the IMR-register, which is is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * the very register we are trying to emulate. The register read back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * is a reasonable heuristic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) at91_rtc_read(AT91_RTC_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) at91_rtc_shadow_imr &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) spin_unlock_irqrestore(&at91_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static u32 at91_rtc_read_imr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (at91_rtc_config->use_shadow_imr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) spin_lock_irqsave(&at91_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mask = at91_rtc_shadow_imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) spin_unlock_irqrestore(&at91_rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mask = at91_rtc_read(AT91_RTC_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * Decode time/date into rtc_time structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void at91_rtc_decodetime(unsigned int timereg, unsigned int calreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int time, date;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* must read twice in case it changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) time = at91_rtc_read(timereg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) date = at91_rtc_read(calreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } while ((time != at91_rtc_read(timereg)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) (date != at91_rtc_read(calreg)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) tm->tm_sec = bcd2bin(FIELD_GET(AT91_RTC_SEC, time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) tm->tm_min = bcd2bin(FIELD_GET(AT91_RTC_MIN, time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) tm->tm_hour = bcd2bin(FIELD_GET(AT91_RTC_HOUR, time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * The Calendar Alarm register does not have a field for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * the year - so these will return an invalid value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) tm->tm_year = bcd2bin(date & AT91_RTC_CENT) * 100; /* century */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) tm->tm_year += bcd2bin(FIELD_GET(AT91_RTC_YEAR, date)); /* year */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tm->tm_wday = bcd2bin(FIELD_GET(AT91_RTC_DAY, date)) - 1; /* day of the week [0-6], Sunday=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) tm->tm_mon = bcd2bin(FIELD_GET(AT91_RTC_MONTH, date)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) tm->tm_mday = bcd2bin(FIELD_GET(AT91_RTC_DATE, date));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Read current time and date in RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) tm->tm_year = tm->tm_year - 1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_dbg(dev, "%s(): %ptR\n", __func__, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Set current time and date in RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned long cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_dbg(dev, "%s(): %ptR\n", __func__, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) wait_for_completion(&at91_rtc_upd_rdy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Stop Time/Calendar from counting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) cr = at91_rtc_read(AT91_RTC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) at91_rtc_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) at91_rtc_write_ier(AT91_RTC_ACKUPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) at91_rtc_write_idr(AT91_RTC_ACKUPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) at91_rtc_write(AT91_RTC_TIMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) FIELD_PREP(AT91_RTC_SEC, bin2bcd(tm->tm_sec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) | FIELD_PREP(AT91_RTC_MIN, bin2bcd(tm->tm_min))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) | FIELD_PREP(AT91_RTC_HOUR, bin2bcd(tm->tm_hour)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) at91_rtc_write(AT91_RTC_CALR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) FIELD_PREP(AT91_RTC_CENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) bin2bcd((tm->tm_year + 1900) / 100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) | FIELD_PREP(AT91_RTC_YEAR, bin2bcd(tm->tm_year % 100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) | FIELD_PREP(AT91_RTC_MONTH, bin2bcd(tm->tm_mon + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) | FIELD_PREP(AT91_RTC_DAY, bin2bcd(tm->tm_wday + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) | FIELD_PREP(AT91_RTC_DATE, bin2bcd(tm->tm_mday)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Restart Time/Calendar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cr = at91_rtc_read(AT91_RTC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_SECEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) at91_rtc_write(AT91_RTC_CR, cr & ~(AT91_RTC_UPDCAL | AT91_RTC_UPDTIM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) at91_rtc_write_ier(AT91_RTC_SECEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Read alarm time and date in RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct rtc_time *tm = &alrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) at91_rtc_decodetime(AT91_RTC_TIMALR, AT91_RTC_CALALR, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) tm->tm_year = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) alrm->enabled = (at91_rtc_read_imr() & AT91_RTC_ALARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev_dbg(dev, "%s(): %ptR %sabled\n", __func__, tm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) alrm->enabled ? "en" : "dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Set alarm time and date in RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct rtc_time tm = alrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) at91_rtc_write_idr(AT91_RTC_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) at91_rtc_write(AT91_RTC_TIMALR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) FIELD_PREP(AT91_RTC_SEC, bin2bcd(alrm->time.tm_sec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) | FIELD_PREP(AT91_RTC_MIN, bin2bcd(alrm->time.tm_min))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) | FIELD_PREP(AT91_RTC_HOUR, bin2bcd(alrm->time.tm_hour))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) | AT91_RTC_HOUREN | AT91_RTC_MINEN | AT91_RTC_SECEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) at91_rtc_write(AT91_RTC_CALALR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) FIELD_PREP(AT91_RTC_MONTH, bin2bcd(alrm->time.tm_mon + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) | FIELD_PREP(AT91_RTC_DATE, bin2bcd(alrm->time.tm_mday))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) | AT91_RTC_DATEEN | AT91_RTC_MTHEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (alrm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) at91_rtc_write_ier(AT91_RTC_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dev_dbg(dev, "%s(): %ptR\n", __func__, &tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_dbg(dev, "%s(): cmd=%08x\n", __func__, enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) at91_rtc_write_ier(AT91_RTC_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) at91_rtc_write_idr(AT91_RTC_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * IRQ handler for the RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct platform_device *pdev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct rtc_device *rtc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int rtsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned long events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) spin_lock(&suspended_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read_imr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (rtsr) { /* this interrupt is shared! Is it ours? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (rtsr & AT91_RTC_ALARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) events |= (RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (rtsr & AT91_RTC_SECEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) complete(&at91_rtc_upd_rdy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) at91_rtc_write_idr(AT91_RTC_SECEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (rtsr & AT91_RTC_ACKUPD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) complete(&at91_rtc_updated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) at91_rtc_write(AT91_RTC_SCCR, rtsr); /* clear status reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) rtc_update_irq(rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_dbg(&pdev->dev, "%s(): num=%ld, events=0x%02lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) __func__, events >> 8, events & 0x000000FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) cached_events |= events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) at91_rtc_write_idr(at91_rtc_imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pm_system_wakeup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) spin_unlock(&suspended_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const struct at91_rtc_config at91rm9200_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const struct at91_rtc_config at91sam9x5_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .use_shadow_imr = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct of_device_id at91_rtc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .compatible = "atmel,at91rm9200-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .data = &at91rm9200_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .compatible = "atmel,at91sam9x5-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .data = &at91sam9x5_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .compatible = "atmel,sama5d4-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .data = &at91rm9200_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .compatible = "atmel,sama5d2-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .data = &at91rm9200_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct rtc_class_ops at91_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .read_time = at91_rtc_readtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .set_time = at91_rtc_settime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .read_alarm = at91_rtc_readalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .set_alarm = at91_rtc_setalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .alarm_irq_enable = at91_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * Initialize and install RTC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int __init at91_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct resource *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) at91_rtc_config = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (!at91_rtc_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev_err(&pdev->dev, "no mmio resource defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) at91_rtc_regs = devm_ioremap(&pdev->dev, regs->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) resource_size(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (!at91_rtc_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(&pdev->dev, "failed to map registers, aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (IS_ERR(rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) sclk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (IS_ERR(sclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return PTR_ERR(sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret = clk_prepare_enable(sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_err(&pdev->dev, "Could not enable slow clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) at91_rtc_write(AT91_RTC_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) at91_rtc_write(AT91_RTC_MR, 0); /* 24 hour mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) AT91_RTC_SECEV | AT91_RTC_TIMEV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) AT91_RTC_CALEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = devm_request_irq(&pdev->dev, irq, at91_rtc_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) IRQF_SHARED | IRQF_COND_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "at91_rtc", pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_err(&pdev->dev, "IRQ %d already in use.\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* cpu init code should really have flagged this device as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * being wake-capable; if it didn't, do that here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!device_can_wakeup(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) rtc->ops = &at91_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) rtc->range_min = RTC_TIMESTAMP_BEGIN_1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) rtc->range_max = RTC_TIMESTAMP_END_2099;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = rtc_register_device(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* enable SECEV interrupt in order to initialize at91_rtc_upd_rdy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) at91_rtc_write_ier(AT91_RTC_SECEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_info(&pdev->dev, "AT91 Real Time Clock driver.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) clk_disable_unprepare(sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * Disable and remove the RTC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int __exit at91_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) AT91_RTC_SECEV | AT91_RTC_TIMEV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) AT91_RTC_CALEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) clk_disable_unprepare(sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void at91_rtc_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) AT91_RTC_SECEV | AT91_RTC_TIMEV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) AT91_RTC_CALEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* AT91RM9200 RTC Power management control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int at91_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* this IRQ is shared with DBGU and other hardware which isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * necessarily doing PM like we are...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) at91_rtc_imr = at91_rtc_read_imr()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) & (AT91_RTC_ALARM|AT91_RTC_SECEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (at91_rtc_imr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (device_may_wakeup(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) enable_irq_wake(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) spin_lock_irqsave(&suspended_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) spin_unlock_irqrestore(&suspended_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) at91_rtc_write_idr(at91_rtc_imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int at91_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct rtc_device *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (at91_rtc_imr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (device_may_wakeup(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) spin_lock_irqsave(&suspended_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (cached_events) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) rtc_update_irq(rtc, 1, cached_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) cached_events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) spin_unlock_irqrestore(&suspended_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) disable_irq_wake(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) at91_rtc_write_ier(at91_rtc_imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static struct platform_driver at91_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .remove = __exit_p(at91_rtc_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .shutdown = at91_rtc_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .name = "at91_rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .pm = &at91_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .of_match_table = of_match_ptr(at91_rtc_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) module_platform_driver_probe(at91_rtc_driver, at91_rtc_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MODULE_AUTHOR("Rick Bronson");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MODULE_DESCRIPTION("RTC driver for Atmel AT91RM9200");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MODULE_ALIAS("platform:at91_rtc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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