^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * A driver for the I2C members of the Abracon AB x8xx RTC family,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * and compatible: AB 1805 and AB 0805
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2014-2015 Macq S.A.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Philippe De Muyter <phdm@macqel.be>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ABX8XX_REG_HTH 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ABX8XX_REG_SC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ABX8XX_REG_MN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ABX8XX_REG_HR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ABX8XX_REG_DA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ABX8XX_REG_MO 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ABX8XX_REG_YR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ABX8XX_REG_WD 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ABX8XX_REG_AHTH 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ABX8XX_REG_ASC 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ABX8XX_REG_AMN 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ABX8XX_REG_AHR 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ABX8XX_REG_ADA 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ABX8XX_REG_AMO 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ABX8XX_REG_AWD 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ABX8XX_REG_STATUS 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ABX8XX_STATUS_AF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ABX8XX_STATUS_BLF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ABX8XX_STATUS_WDT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ABX8XX_REG_CTRL1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ABX8XX_CTRL_WRITE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ABX8XX_CTRL_ARST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ABX8XX_CTRL_12_24 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ABX8XX_REG_CTRL2 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ABX8XX_CTRL2_RSVD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ABX8XX_REG_IRQ 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ABX8XX_IRQ_AIE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ABX8XX_IRQ_IM_1_4 (0x3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ABX8XX_REG_CD_TIMER_CTL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ABX8XX_REG_OSC 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ABX8XX_OSC_FOS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ABX8XX_OSC_BOS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ABX8XX_OSC_ACAL_512 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ABX8XX_OSC_ACAL_1024 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ABX8XX_OSC_OSEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ABX8XX_REG_OSS 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ABX8XX_OSS_OF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ABX8XX_OSS_OMODE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ABX8XX_REG_WDT 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ABX8XX_WDT_WDS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ABX8XX_WDT_BMB_MASK 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ABX8XX_WDT_BMB_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ABX8XX_WDT_MAX_TIME (ABX8XX_WDT_BMB_MASK >> ABX8XX_WDT_BMB_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ABX8XX_WDT_WRB_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ABX8XX_WDT_WRB_1HZ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ABX8XX_REG_CFG_KEY 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ABX8XX_CFG_KEY_OSC 0xa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ABX8XX_CFG_KEY_MISC 0x9d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ABX8XX_REG_ID0 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ABX8XX_REG_OUT_CTRL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ABX8XX_OUT_CTRL_EXDS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ABX8XX_REG_TRICKLE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ABX8XX_TRICKLE_CHARGE_ENABLE 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ABX8XX_TRICKLE_STANDARD_DIODE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ABX8XX_TRICKLE_SCHOTTKY_DIODE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static u8 trickle_resistors[] = {0, 3, 6, 11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enum abx80x_chip {AB0801, AB0803, AB0804, AB0805,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) AB1801, AB1803, AB1804, AB1805, RV1805, ABX80X};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct abx80x_cap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u16 pn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) bool has_tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) bool has_wdog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct abx80x_cap abx80x_caps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [AB0801] = {.pn = 0x0801},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [AB0803] = {.pn = 0x0803},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [AB0804] = {.pn = 0x0804, .has_tc = true, .has_wdog = true},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [AB0805] = {.pn = 0x0805, .has_tc = true, .has_wdog = true},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [AB1801] = {.pn = 0x1801},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [AB1803] = {.pn = 0x1803},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [AB1804] = {.pn = 0x1804, .has_tc = true, .has_wdog = true},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [AB1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [RV1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [ABX80X] = {.pn = 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct abx80x_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct watchdog_device wdog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int abx80x_is_rc_mode(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (flags < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) "Failed to read autocalibration attribute\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return (flags & ABX8XX_OSS_OMODE) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int abx80x_enable_trickle_charger(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u8 trickle_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Write the configuration key register to enable access to the Trickle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ABX8XX_CFG_KEY_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_err(&client->dev, "Unable to write configuration key\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) err = i2c_smbus_write_byte_data(client, ABX8XX_REG_TRICKLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ABX8XX_TRICKLE_CHARGE_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) trickle_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dev_err(&client->dev, "Unable to write trickle register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int abx80x_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned char buf[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int err, flags, rc_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Read the Oscillator Failure only in XT mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) rc_mode = abx80x_is_rc_mode(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (rc_mode < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return rc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!rc_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (flags < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (flags & ABX8XX_OSS_OF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_err(dev, "Oscillator failure, data is invalid.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) err = i2c_smbus_read_i2c_block_data(client, ABX8XX_REG_HTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) sizeof(buf), buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dev_err(&client->dev, "Unable to read date\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) tm->tm_sec = bcd2bin(buf[ABX8XX_REG_SC] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) tm->tm_min = bcd2bin(buf[ABX8XX_REG_MN] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tm->tm_hour = bcd2bin(buf[ABX8XX_REG_HR] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) tm->tm_wday = buf[ABX8XX_REG_WD] & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) tm->tm_mday = bcd2bin(buf[ABX8XX_REG_DA] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) tm->tm_mon = bcd2bin(buf[ABX8XX_REG_MO] & 0x1F) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) tm->tm_year = bcd2bin(buf[ABX8XX_REG_YR]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int abx80x_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned char buf[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int err, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (tm->tm_year < 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) buf[ABX8XX_REG_HTH] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) buf[ABX8XX_REG_SC] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) buf[ABX8XX_REG_MN] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) buf[ABX8XX_REG_HR] = bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) buf[ABX8XX_REG_DA] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) buf[ABX8XX_REG_MO] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) buf[ABX8XX_REG_YR] = bin2bcd(tm->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) buf[ABX8XX_REG_WD] = tm->tm_wday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) err = i2c_smbus_write_i2c_block_data(client, ABX8XX_REG_HTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) sizeof(buf), buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev_err(&client->dev, "Unable to write to date registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Clear the OF bit of Oscillator Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (flags < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) err = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) flags & ~ABX8XX_OSS_OF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev_err(&client->dev, "Unable to write oscillator status register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static irqreturn_t abx80x_handle_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct i2c_client *client = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct abx80x_priv *priv = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct rtc_device *rtc = priv->rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) status = i2c_smbus_read_byte_data(client, ABX8XX_REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (status & ABX8XX_STATUS_AF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * It is unclear if we'll get an interrupt before the external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * reset kicks in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (status & ABX8XX_STATUS_WDT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev_alert(&client->dev, "watchdog timeout interrupt.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) i2c_smbus_write_byte_data(client, ABX8XX_REG_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int abx80x_read_alarm(struct device *dev, struct rtc_wkalrm *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned char buf[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int irq_mask, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (client->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) err = i2c_smbus_read_i2c_block_data(client, ABX8XX_REG_ASC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) sizeof(buf), buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) irq_mask = i2c_smbus_read_byte_data(client, ABX8XX_REG_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (irq_mask < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) t->time.tm_sec = bcd2bin(buf[0] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) t->time.tm_min = bcd2bin(buf[1] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) t->time.tm_hour = bcd2bin(buf[2] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) t->time.tm_mday = bcd2bin(buf[3] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) t->time.tm_mon = bcd2bin(buf[4] & 0x1F) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) t->time.tm_wday = buf[5] & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) t->enabled = !!(irq_mask & ABX8XX_IRQ_AIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) t->pending = (buf[6] & ABX8XX_STATUS_AF) && t->enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int abx80x_set_alarm(struct device *dev, struct rtc_wkalrm *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u8 alarm[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (client->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) alarm[0] = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) alarm[1] = bin2bcd(t->time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) alarm[2] = bin2bcd(t->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) alarm[3] = bin2bcd(t->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) alarm[4] = bin2bcd(t->time.tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) alarm[5] = bin2bcd(t->time.tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) err = i2c_smbus_write_i2c_block_data(client, ABX8XX_REG_AHTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) sizeof(alarm), alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dev_err(&client->dev, "Unable to write alarm registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (t->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) err = i2c_smbus_write_byte_data(client, ABX8XX_REG_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) (ABX8XX_IRQ_IM_1_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ABX8XX_IRQ_AIE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int abx80x_rtc_set_autocalibration(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int autocalibration)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int retval, flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if ((autocalibration != 0) && (autocalibration != 1024) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) (autocalibration != 512)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev_err(dev, "autocalibration value outside permitted range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (flags < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (autocalibration == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) flags &= ~(ABX8XX_OSC_ACAL_512 | ABX8XX_OSC_ACAL_1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) } else if (autocalibration == 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* 1024 autocalibration is 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) flags |= ABX8XX_OSC_ACAL_1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) flags &= ~(ABX8XX_OSC_ACAL_512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* 512 autocalibration is 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) flags |= (ABX8XX_OSC_ACAL_1024 | ABX8XX_OSC_ACAL_512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Unlock write access to Oscillator Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ABX8XX_CFG_KEY_OSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_err(dev, "Failed to write CONFIG_KEY register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSC, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int abx80x_rtc_get_autocalibration(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int flags = 0, autocalibration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (flags < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (flags & ABX8XX_OSC_ACAL_512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) autocalibration = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) else if (flags & ABX8XX_OSC_ACAL_1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) autocalibration = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) autocalibration = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return autocalibration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static ssize_t autocalibration_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned long autocalibration = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) retval = kstrtoul(buf, 10, &autocalibration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_err(dev, "Failed to store RTC autocalibration attribute\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) retval = abx80x_rtc_set_autocalibration(dev->parent, autocalibration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return retval ? retval : count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static ssize_t autocalibration_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int autocalibration = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) autocalibration = abx80x_rtc_get_autocalibration(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (autocalibration < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev_err(dev, "Failed to read RTC autocalibration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) sprintf(buf, "0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return autocalibration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return sprintf(buf, "%d\n", autocalibration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static DEVICE_ATTR_RW(autocalibration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static ssize_t oscillator_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct i2c_client *client = to_i2c_client(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int retval, flags, rc_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (strncmp(buf, "rc", 2) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) rc_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) } else if (strncmp(buf, "xtal", 4) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) rc_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_err(dev, "Oscillator selection value outside permitted ones\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (flags < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (rc_mode == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) flags &= ~(ABX8XX_OSC_OSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) flags |= (ABX8XX_OSC_OSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Unlock write access on Oscillator Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ABX8XX_CFG_KEY_OSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dev_err(dev, "Failed to write CONFIG_KEY register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSC, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_err(dev, "Failed to write Oscillator Control register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return retval ? retval : count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static ssize_t oscillator_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int rc_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct i2c_client *client = to_i2c_client(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) rc_mode = abx80x_is_rc_mode(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (rc_mode < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev_err(dev, "Failed to read RTC oscillator selection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) sprintf(buf, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return rc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (rc_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return sprintf(buf, "rc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return sprintf(buf, "xtal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static DEVICE_ATTR_RW(oscillator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static struct attribute *rtc_calib_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) &dev_attr_autocalibration.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) &dev_attr_oscillator.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const struct attribute_group rtc_calib_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .attrs = rtc_calib_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int abx80x_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) err = i2c_smbus_write_byte_data(client, ABX8XX_REG_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) (ABX8XX_IRQ_IM_1_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ABX8XX_IRQ_AIE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) err = i2c_smbus_write_byte_data(client, ABX8XX_REG_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ABX8XX_IRQ_IM_1_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int abx80x_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int status, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case RTC_VL_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) status = i2c_smbus_read_byte_data(client, ABX8XX_REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) tmp = status & ABX8XX_STATUS_BLF ? RTC_VL_BACKUP_LOW : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return put_user(tmp, (unsigned int __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case RTC_VL_CLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) status = i2c_smbus_read_byte_data(client, ABX8XX_REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) status &= ~ABX8XX_STATUS_BLF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) tmp = i2c_smbus_write_byte_data(client, ABX8XX_REG_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static const struct rtc_class_ops abx80x_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .read_time = abx80x_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .set_time = abx80x_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .read_alarm = abx80x_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .set_alarm = abx80x_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .alarm_irq_enable = abx80x_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .ioctl = abx80x_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int abx80x_dt_trickle_cfg(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct device_node *np = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) const char *diode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) int trickle_cfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = of_property_read_string(np, "abracon,tc-diode", &diode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (!strcmp(diode, "standard")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) trickle_cfg |= ABX8XX_TRICKLE_STANDARD_DIODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) } else if (!strcmp(diode, "schottky")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) trickle_cfg |= ABX8XX_TRICKLE_SCHOTTKY_DIODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dev_dbg(&client->dev, "Invalid tc-diode value: %s\n", diode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = of_property_read_u32(np, "abracon,tc-resistor", &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) for (i = 0; i < sizeof(trickle_resistors); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (trickle_resistors[i] == tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (i == sizeof(trickle_resistors)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_dbg(&client->dev, "Invalid tc-resistor value: %u\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return (trickle_cfg | i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #ifdef CONFIG_WATCHDOG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static inline u8 timeout_bits(unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return ((timeout << ABX8XX_WDT_BMB_SHIFT) & ABX8XX_WDT_BMB_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ABX8XX_WDT_WRB_1HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static int __abx80x_wdog_set_timeout(struct watchdog_device *wdog,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct abx80x_priv *priv = watchdog_get_drvdata(wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u8 val = ABX8XX_WDT_WDS | timeout_bits(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * Writing any timeout to the WDT register resets the watchdog timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * Writing 0 disables it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return i2c_smbus_write_byte_data(priv->client, ABX8XX_REG_WDT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static int abx80x_wdog_set_timeout(struct watchdog_device *wdog,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) unsigned int new_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (watchdog_hw_running(wdog))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) err = __abx80x_wdog_set_timeout(wdog, new_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (err == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) wdog->timeout = new_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int abx80x_wdog_ping(struct watchdog_device *wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return __abx80x_wdog_set_timeout(wdog, wdog->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int abx80x_wdog_start(struct watchdog_device *wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return __abx80x_wdog_set_timeout(wdog, wdog->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int abx80x_wdog_stop(struct watchdog_device *wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return __abx80x_wdog_set_timeout(wdog, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static const struct watchdog_info abx80x_wdog_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .identity = "abx80x watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static const struct watchdog_ops abx80x_wdog_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .start = abx80x_wdog_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .stop = abx80x_wdog_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .ping = abx80x_wdog_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .set_timeout = abx80x_wdog_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static int abx80x_setup_watchdog(struct abx80x_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) priv->wdog.parent = &priv->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) priv->wdog.ops = &abx80x_wdog_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) priv->wdog.info = &abx80x_wdog_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) priv->wdog.min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) priv->wdog.max_timeout = ABX8XX_WDT_MAX_TIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) priv->wdog.timeout = ABX8XX_WDT_MAX_TIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) watchdog_set_drvdata(&priv->wdog, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return devm_watchdog_register_device(&priv->client->dev, &priv->wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static int abx80x_setup_watchdog(struct abx80x_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int abx80x_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct device_node *np = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct abx80x_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) int i, data, err, trickle_cfg = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) char buf[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) unsigned int part = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) unsigned int partnumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) unsigned int majrev, minrev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) unsigned int lot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) unsigned int wafer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) unsigned int uid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) err = i2c_smbus_read_i2c_block_data(client, ABX8XX_REG_ID0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) sizeof(buf), buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dev_err(&client->dev, "Unable to read partnumber\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) partnumber = (buf[0] << 8) | buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) majrev = buf[2] >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) minrev = buf[2] & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) lot = ((buf[4] & 0x80) << 2) | ((buf[6] & 0x80) << 1) | buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) uid = ((buf[4] & 0x7f) << 8) | buf[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) wafer = (buf[6] & 0x7c) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) dev_info(&client->dev, "model %04x, revision %u.%u, lot %x, wafer %x, uid %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) partnumber, majrev, minrev, lot, wafer, uid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) data = i2c_smbus_read_byte_data(client, ABX8XX_REG_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (data < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) dev_err(&client->dev, "Unable to read control register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ((data & ~(ABX8XX_CTRL_12_24 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ABX8XX_CTRL_ARST)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ABX8XX_CTRL_WRITE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_err(&client->dev, "Unable to write control register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* Configure RV1805 specifics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (part == RV1805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * Avoid accidentally entering test mode. This can happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * on the RV1805 in case the reserved bit 5 in control2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * register is set. RV-1805-C3 datasheet indicates that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * the bit should be cleared in section 11h - Control2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) data = i2c_smbus_read_byte_data(client, ABX8XX_REG_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (data < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) "Unable to read control2 register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) data & ~ABX8XX_CTRL2_RSVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "Unable to write control2 register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * Avoid extra power leakage. The RV1805 uses smaller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * 10pin package and the EXTI input is not present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * Disable it to avoid leakage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) data = i2c_smbus_read_byte_data(client, ABX8XX_REG_OUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (data < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) "Unable to read output control register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * Write the configuration key register to enable access to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * the config2 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ABX8XX_CFG_KEY_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) "Unable to write configuration key\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) err = i2c_smbus_write_byte_data(client, ABX8XX_REG_OUT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) data | ABX8XX_OUT_CTRL_EXDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) "Unable to write output control register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* part autodetection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (part == ABX80X) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) for (i = 0; abx80x_caps[i].pn; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (partnumber == abx80x_caps[i].pn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (abx80x_caps[i].pn == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) dev_err(&client->dev, "Unknown part: %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) partnumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) part = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (partnumber != abx80x_caps[part].pn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dev_err(&client->dev, "partnumber mismatch %04x != %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) partnumber, abx80x_caps[part].pn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (np && abx80x_caps[part].has_tc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) trickle_cfg = abx80x_dt_trickle_cfg(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (trickle_cfg > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_info(&client->dev, "Enabling trickle charger: %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) trickle_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) abx80x_enable_trickle_charger(client, trickle_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CD_TIMER_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) BIT(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (priv == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) priv->rtc = devm_rtc_allocate_device(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (IS_ERR(priv->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return PTR_ERR(priv->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) priv->rtc->ops = &abx80x_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) priv->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) i2c_set_clientdata(client, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (abx80x_caps[part].has_wdog) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) err = abx80x_setup_watchdog(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dev_info(&client->dev, "IRQ %d supplied\n", client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) err = devm_request_threaded_irq(&client->dev, client->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) abx80x_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) IRQF_SHARED | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) "abx8xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dev_err(&client->dev, "unable to request IRQ, alarms disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) client->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) err = rtc_add_group(priv->rtc, &rtc_calib_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dev_err(&client->dev, "Failed to create sysfs group: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return rtc_register_device(priv->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static const struct i2c_device_id abx80x_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) { "abx80x", ABX80X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) { "ab0801", AB0801 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) { "ab0803", AB0803 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) { "ab0804", AB0804 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) { "ab0805", AB0805 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) { "ab1801", AB1801 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) { "ab1803", AB1803 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) { "ab1804", AB1804 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) { "ab1805", AB1805 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) { "rv1805", RV1805 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) MODULE_DEVICE_TABLE(i2c, abx80x_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static const struct of_device_id abx80x_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .compatible = "abracon,abx80x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .data = (void *)ABX80X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .compatible = "abracon,ab0801",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .data = (void *)AB0801
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .compatible = "abracon,ab0803",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .data = (void *)AB0803
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .compatible = "abracon,ab0804",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .data = (void *)AB0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .compatible = "abracon,ab0805",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .data = (void *)AB0805
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .compatible = "abracon,ab1801",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .data = (void *)AB1801
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .compatible = "abracon,ab1803",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .data = (void *)AB1803
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .compatible = "abracon,ab1804",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .data = (void *)AB1804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .compatible = "abracon,ab1805",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .data = (void *)AB1805
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .compatible = "microcrystal,rv1805",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .data = (void *)RV1805
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) MODULE_DEVICE_TABLE(of, abx80x_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static struct i2c_driver abx80x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .name = "rtc-abx80x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .of_match_table = of_match_ptr(abx80x_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .probe = abx80x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .id_table = abx80x_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) module_i2c_driver(abx80x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) MODULE_AUTHOR("Philippe De Muyter <phdm@macqel.be>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) MODULE_DESCRIPTION("Abracon ABX80X RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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