Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2007-2009 ST-Ericsson AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * RTC clock driver for the AB3100 Analog Baseband Chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Linus Walleij <linus.walleij@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mfd/abx500.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /* Clock rate in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define AB3100_RTC_CLOCK_RATE	32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * The AB3100 RTC registers. These are the same for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * AB3000 and AB3100.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * Control register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * Bit 0: RTC Monitor cleared=0, active=1, if you set it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *        to 1 it remains active until RTC power is lost.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * Bit 1: 32 kHz Oscillator, 0 = on, 1 = bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * Bit 2: Alarm on, 0 = off, 1 = on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * Bit 3: 32 kHz buffer disabling, 0 = enabled, 1 = disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AB3100_RTC		0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* default setting, buffer disabled, alarm on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define RTC_SETTING		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* Alarm when AL0-AL3 == TI0-TI3  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AB3100_AL0		0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AB3100_AL1		0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AB3100_AL2		0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AB3100_AL3		0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* This 48-bit register that counts up at 32768 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AB3100_TI0		0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AB3100_TI1		0x5b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AB3100_TI2		0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define AB3100_TI3		0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define AB3100_TI4		0x5e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define AB3100_TI5		0x5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * RTC clock functions and device struct declaration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static int ab3100_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u8 regs[] = {AB3100_TI0, AB3100_TI1, AB3100_TI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		     AB3100_TI3, AB3100_TI4, AB3100_TI5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned char buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u64 hw_counter = rtc_tm_to_time64(tm) * AB3100_RTC_CLOCK_RATE * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	buf[0] = (hw_counter) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	buf[1] = (hw_counter >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	buf[2] = (hw_counter >> 16) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	buf[3] = (hw_counter >> 24) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	buf[4] = (hw_counter >> 32) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	buf[5] = (hw_counter >> 40) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	for (i = 0; i < 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		err = abx500_set_register_interruptible(dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 							regs[i], buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	/* Set the flag to mark that the clock is now set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	return abx500_mask_and_set_register_interruptible(dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 							  AB3100_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 							  0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static int ab3100_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	time64_t time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u8 rtcval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	err = abx500_get_register_interruptible(dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 						AB3100_RTC, &rtcval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (!(rtcval & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		dev_info(dev, "clock not set (lost power)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		u64 hw_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		/* Read out time registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		err = abx500_get_register_page_interruptible(dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 							     AB3100_TI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 							     buf, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		if (err != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		hw_counter = ((u64) buf[5] << 40) | ((u64) buf[4] << 32) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			((u64) buf[3] << 24) | ((u64) buf[2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			((u64) buf[1] << 8) | (u64) buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		time = hw_counter / (u64) (AB3100_RTC_CLOCK_RATE * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	rtc_time64_to_tm(time, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int ab3100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	time64_t time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	u64 hw_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u8 rtcval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* Figure out if alarm is enabled or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	err = abx500_get_register_interruptible(dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 						AB3100_RTC, &rtcval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (rtcval & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		alarm->enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		alarm->enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	/* No idea how this could be represented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	alarm->pending = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/* Read out alarm registers, only 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	err = abx500_get_register_page_interruptible(dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 						     AB3100_AL0, buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	hw_counter = ((u64) buf[3] << 40) | ((u64) buf[2] << 32) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		((u64) buf[1] << 24) | ((u64) buf[0] << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	time = hw_counter / (u64) (AB3100_RTC_CLOCK_RATE * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	rtc_time64_to_tm(time, &alarm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return rtc_valid_tm(&alarm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int ab3100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	u8 regs[] = {AB3100_AL0, AB3100_AL1, AB3100_AL2, AB3100_AL3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	unsigned char buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	time64_t secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	u64 hw_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	secs = rtc_tm_to_time64(&alarm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	hw_counter = secs * AB3100_RTC_CLOCK_RATE * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	buf[0] = (hw_counter >> 16) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	buf[1] = (hw_counter >> 24) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	buf[2] = (hw_counter >> 32) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	buf[3] = (hw_counter >> 40) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/* Set the alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		err = abx500_set_register_interruptible(dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 							regs[i], buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	/* Then enable the alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return abx500_mask_and_set_register_interruptible(dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 							  AB3100_RTC, (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 							  alarm->enabled << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int ab3100_rtc_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	 * It's not possible to enable/disable the alarm IRQ for this RTC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	 * It does not actually trigger any IRQ: instead its only function is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	 * to power up the system, if it wasn't on. This will manifest as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * a "power up cause" in the AB3100 power driver (battery charging etc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 * and need to be handled there instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return abx500_mask_and_set_register_interruptible(dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 						    AB3100_RTC, (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 						    1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return abx500_mask_and_set_register_interruptible(dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 						    AB3100_RTC, (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 						    0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const struct rtc_class_ops ab3100_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.read_time	= ab3100_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.set_time	= ab3100_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.read_alarm	= ab3100_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.set_alarm	= ab3100_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.alarm_irq_enable = ab3100_rtc_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int __init ab3100_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	u8 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/* The first RTC register needs special treatment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	err = abx500_get_register_interruptible(&pdev->dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 						AB3100_RTC, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		dev_err(&pdev->dev, "unable to read RTC register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if ((regval & 0xFE) != RTC_SETTING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		dev_warn(&pdev->dev, "not default value in RTC reg 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			 regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if ((regval & 1) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		 * Set bit to detect power loss.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		 * This bit remains until RTC power is lost.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		regval = 1 | RTC_SETTING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		err = abx500_set_register_interruptible(&pdev->dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 							AB3100_RTC, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		/* Ignore any error on this write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (IS_ERR(rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	rtc->ops = &ab3100_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/* 48bit counter at (AB3100_RTC_CLOCK_RATE * 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	rtc->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	return rtc_register_device(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static struct platform_driver ab3100_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		.name = "ab3100-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) module_platform_driver_probe(ab3100_rtc_driver, ab3100_rtc_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MODULE_DESCRIPTION("AB3100 RTC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MODULE_LICENSE("GPL");