Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Real Time Clock driver for AB-RTCMC-32.768kHz-EOZ9 chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2019 Orolia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define ABEOZ9_REG_CTRL1		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define ABEOZ9_REG_CTRL1_MASK		GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define ABEOZ9_REG_CTRL1_WE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define ABEOZ9_REG_CTRL1_TE		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define ABEOZ9_REG_CTRL1_TAR		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define ABEOZ9_REG_CTRL1_EERE		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define ABEOZ9_REG_CTRL1_SRON		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define ABEOZ9_REG_CTRL1_TD0		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define ABEOZ9_REG_CTRL1_TD1		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define ABEOZ9_REG_CTRL1_CLKINT		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ABEOZ9_REG_CTRL_INT		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ABEOZ9_REG_CTRL_INT_AIE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ABEOZ9_REG_CTRL_INT_TIE		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ABEOZ9_REG_CTRL_INT_V1IE	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ABEOZ9_REG_CTRL_INT_V2IE	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ABEOZ9_REG_CTRL_INT_SRIE	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define ABEOZ9_REG_CTRL_INT_FLAG	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ABEOZ9_REG_CTRL_INT_FLAG_AF	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ABEOZ9_REG_CTRL_INT_FLAG_TF	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define ABEOZ9_REG_CTRL_INT_FLAG_V1IF	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define ABEOZ9_REG_CTRL_INT_FLAG_V2IF	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define ABEOZ9_REG_CTRL_INT_FLAG_SRF	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ABEOZ9_REG_CTRL_STATUS		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ABEOZ9_REG_CTRL_STATUS_V1F	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ABEOZ9_REG_CTRL_STATUS_V2F	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define ABEOZ9_REG_CTRL_STATUS_SR	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define ABEOZ9_REG_CTRL_STATUS_PON	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define ABEOZ9_REG_CTRL_STATUS_EEBUSY	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define ABEOZ9_REG_SEC			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define ABEOZ9_REG_MIN			0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define ABEOZ9_REG_HOURS		0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define ABEOZ9_HOURS_PM			BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define ABEOZ9_REG_DAYS			0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define ABEOZ9_REG_WEEKDAYS		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define ABEOZ9_REG_MONTHS		0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define ABEOZ9_REG_YEARS		0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define ABEOZ9_SEC_LEN			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define ABEOZ9_REG_REG_TEMP		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define ABEOZ953_TEMP_MAX		120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define ABEOZ953_TEMP_MIN		-60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define ABEOZ9_REG_EEPROM		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define ABEOZ9_REG_EEPROM_MASK		GENMASK(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define ABEOZ9_REG_EEPROM_THP		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define ABEOZ9_REG_EEPROM_THE		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define ABEOZ9_REG_EEPROM_FD0		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define ABEOZ9_REG_EEPROM_FD1		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define ABEOZ9_REG_EEPROM_R1K		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define ABEOZ9_REG_EEPROM_R5K		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define ABEOZ9_REG_EEPROM_R20K		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define ABEOZ9_REG_EEPROM_R80K		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) struct abeoz9_rtc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static int abeoz9_check_validity(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct regmap *regmap = data->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	ret = regmap_read(regmap, ABEOZ9_REG_CTRL_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			"unable to get CTRL_STATUS register (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (val & ABEOZ9_REG_CTRL_STATUS_PON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		dev_warn(dev, "power-on reset detected, date is invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (val & ABEOZ9_REG_CTRL_STATUS_V1F) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			 "voltage drops below VLOW1 threshold, date is invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if ((val & ABEOZ9_REG_CTRL_STATUS_V2F)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			 "voltage drops below VLOW2 threshold, date is invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int abeoz9_reset_validity(struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	return regmap_update_bits(regmap, ABEOZ9_REG_CTRL_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 				  ABEOZ9_REG_CTRL_STATUS_V1F |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 				  ABEOZ9_REG_CTRL_STATUS_V2F |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 				  ABEOZ9_REG_CTRL_STATUS_PON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 				  0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int abeoz9_rtc_get_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u8 regs[ABEOZ9_SEC_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	ret = abeoz9_check_validity(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	ret = regmap_bulk_read(data->regmap, ABEOZ9_REG_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			       regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			       sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		dev_err(dev, "reading RTC time failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	tm->tm_sec = bcd2bin(regs[ABEOZ9_REG_SEC - ABEOZ9_REG_SEC] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	tm->tm_min = bcd2bin(regs[ABEOZ9_REG_MIN - ABEOZ9_REG_SEC] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] & ABEOZ9_HOURS_PM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		tm->tm_hour =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			bcd2bin(regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		if (regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] & ABEOZ9_HOURS_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			tm->tm_hour += 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		tm->tm_hour = bcd2bin(regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	tm->tm_mday = bcd2bin(regs[ABEOZ9_REG_DAYS - ABEOZ9_REG_SEC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	tm->tm_wday = bcd2bin(regs[ABEOZ9_REG_WEEKDAYS - ABEOZ9_REG_SEC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	tm->tm_mon  = bcd2bin(regs[ABEOZ9_REG_MONTHS - ABEOZ9_REG_SEC]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	tm->tm_year = bcd2bin(regs[ABEOZ9_REG_YEARS - ABEOZ9_REG_SEC]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int abeoz9_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct regmap *regmap = data->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u8 regs[ABEOZ9_SEC_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	regs[ABEOZ9_REG_SEC - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	regs[ABEOZ9_REG_MIN - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	regs[ABEOZ9_REG_DAYS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	regs[ABEOZ9_REG_WEEKDAYS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	regs[ABEOZ9_REG_MONTHS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	regs[ABEOZ9_REG_YEARS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	ret = regmap_bulk_write(data->regmap, ABEOZ9_REG_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 				regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 				sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		dev_err(dev, "set RTC time failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return abeoz9_reset_validity(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int abeoz9_trickle_parse_dt(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	u32 ohms = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (of_property_read_u32(node, "trickle-resistor-ohms", &ohms))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	switch (ohms) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	case 1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		return ABEOZ9_REG_EEPROM_R1K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	case 5000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return ABEOZ9_REG_EEPROM_R5K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	case 20000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		return ABEOZ9_REG_EEPROM_R20K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	case 80000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return ABEOZ9_REG_EEPROM_R80K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int abeoz9_rtc_setup(struct device *dev, struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct regmap *regmap = data->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	/* Enable Self Recovery, Clock for Watch and EEPROM refresh functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	ret = regmap_update_bits(regmap, ABEOZ9_REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 				 ABEOZ9_REG_CTRL1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 				 ABEOZ9_REG_CTRL1_WE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 				 ABEOZ9_REG_CTRL1_EERE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				 ABEOZ9_REG_CTRL1_SRON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		dev_err(dev, "unable to set CTRL_1 register (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	ret = regmap_write(regmap, ABEOZ9_REG_CTRL_INT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			"unable to set control CTRL_INT register (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	ret = regmap_write(regmap, ABEOZ9_REG_CTRL_INT_FLAG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			"unable to set control CTRL_INT_FLAG register (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	ret = abeoz9_trickle_parse_dt(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	/* Enable built-in termometer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	ret |= ABEOZ9_REG_EEPROM_THE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	ret = regmap_update_bits(regmap, ABEOZ9_REG_EEPROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 				 ABEOZ9_REG_EEPROM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 				 ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		dev_err(dev, "unable to set EEPROM register (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const struct rtc_class_ops rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.read_time = abeoz9_rtc_get_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.set_time  = abeoz9_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const struct regmap_config abeoz9_rtc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #if IS_REACHABLE(CONFIG_HWMON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int abeoz9z3_temp_read(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			      enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			      u32 attr, int channel, long *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct regmap *regmap = data->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	ret = regmap_read(regmap, ABEOZ9_REG_CTRL_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if ((val & ABEOZ9_REG_CTRL_STATUS_V1F) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	    (val & ABEOZ9_REG_CTRL_STATUS_V2F)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			"thermometer might be disabled due to low voltage\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		ret = regmap_read(regmap, ABEOZ9_REG_REG_TEMP, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		*temp = 1000 * (val + ABEOZ953_TEMP_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		*temp = 1000 * ABEOZ953_TEMP_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		*temp = 1000 * ABEOZ953_TEMP_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static umode_t abeoz9_is_visible(const void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 				 enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 				 u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const u32 abeoz9_chip_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	HWMON_C_REGISTER_TZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const struct hwmon_channel_info abeoz9_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.type = hwmon_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.config = abeoz9_chip_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const u32 abeoz9_temp_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct hwmon_channel_info abeoz9_temp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.type = hwmon_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	.config = abeoz9_temp_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const struct hwmon_channel_info *abeoz9_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	&abeoz9_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	&abeoz9_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct hwmon_ops abeoz9_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	.is_visible = abeoz9_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	.read = abeoz9z3_temp_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct hwmon_chip_info abeoz9_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	.ops = &abeoz9_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	.info = abeoz9_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void abeoz9_hwmon_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 				  struct abeoz9_rtc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	data->hwmon_dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		devm_hwmon_device_register_with_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 						     "abeoz9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 						     data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 						     &abeoz9_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 						     NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	if (IS_ERR(data->hwmon_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		dev_warn(dev, "unable to register hwmon device %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 			 PTR_ERR(data->hwmon_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static void abeoz9_hwmon_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 				  struct abeoz9_rtc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int abeoz9_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	struct abeoz9_rtc_data *data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 				     I2C_FUNC_SMBUS_BYTE_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 				     I2C_FUNC_SMBUS_I2C_BLOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	regmap = devm_regmap_init_i2c(client, &abeoz9_rtc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		ret = PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		dev_err(dev, "regmap allocation failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	data->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	dev_set_drvdata(dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	ret = abeoz9_rtc_setup(dev, client->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	data->rtc = devm_rtc_allocate_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	ret = PTR_ERR_OR_ZERO(data->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	data->rtc->ops = &rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	data->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	data->rtc->range_max = RTC_TIMESTAMP_END_2099;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	ret = rtc_register_device(data->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	abeoz9_hwmon_register(dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const struct of_device_id abeoz9_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	{ .compatible = "abracon,abeoz9" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MODULE_DEVICE_TABLE(of, abeoz9_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static const struct i2c_device_id abeoz9_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	{ "abeoz9", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static struct i2c_driver abeoz9_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		.name = "rtc-ab-eoz9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		.of_match_table = of_match_ptr(abeoz9_dt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	.probe	  = abeoz9_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	.id_table = abeoz9_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) module_i2c_driver(abeoz9_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MODULE_AUTHOR("Artem Panfilov <panfilov.artyom@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MODULE_DESCRIPTION("Abracon AB-RTCMC-32.768kHz-EOZ9 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MODULE_LICENSE("GPL");