^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * rtc-ab-b5ze-s3 - Driver for Abracon AB-RTCMC-32.768Khz-B5ZE-S3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * I2C RTC / Alarm chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Detailed datasheet of the chip is available here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * https://www.abracon.com/realtimeclock/AB-RTCMC-32.768kHz-B5ZE-S3-Application-Manual.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This work is based on ISL12057 driver (drivers/rtc/rtc-isl12057.c).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRV_NAME "rtc-ab-b5ze-s3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Control section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ABB5ZES3_REG_CTRL1 0x00 /* Control 1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ABB5ZES3_REG_CTRL1_CIE BIT(0) /* Pulse interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ABB5ZES3_REG_CTRL1_AIE BIT(1) /* Alarm interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ABB5ZES3_REG_CTRL1_SIE BIT(2) /* Second interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ABB5ZES3_REG_CTRL1_PM BIT(3) /* 24h/12h mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ABB5ZES3_REG_CTRL1_SR BIT(4) /* Software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ABB5ZES3_REG_CTRL1_STOP BIT(5) /* RTC circuit enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ABB5ZES3_REG_CTRL1_CAP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ABB5ZES3_REG_CTRL2 0x01 /* Control 2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ABB5ZES3_REG_CTRL2_CTBIE BIT(0) /* Countdown timer B int. enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ABB5ZES3_REG_CTRL2_CTAIE BIT(1) /* Countdown timer A int. enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ABB5ZES3_REG_CTRL2_WTAIE BIT(2) /* Watchdog timer A int. enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ABB5ZES3_REG_CTRL2_AF BIT(3) /* Alarm interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ABB5ZES3_REG_CTRL2_SF BIT(4) /* Second interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ABB5ZES3_REG_CTRL2_CTBF BIT(5) /* Countdown timer B int. status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ABB5ZES3_REG_CTRL2_CTAF BIT(6) /* Countdown timer A int. status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ABB5ZES3_REG_CTRL2_WTAF BIT(7) /* Watchdog timer A int. status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ABB5ZES3_REG_CTRL3 0x02 /* Control 3 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ABB5ZES3_REG_CTRL3_PM2 BIT(7) /* Power Management bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ABB5ZES3_REG_CTRL3_PM1 BIT(6) /* Power Management bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ABB5ZES3_REG_CTRL3_PM0 BIT(5) /* Power Management bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ABB5ZES3_REG_CTRL3_BSF BIT(3) /* Battery switchover int. status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ABB5ZES3_REG_CTRL3_BLF BIT(2) /* Battery low int. status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ABB5ZES3_REG_CTRL3_BSIE BIT(1) /* Battery switchover int. enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ABB5ZES3_REG_CTRL3_BLIE BIT(0) /* Battery low int. enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ABB5ZES3_CTRL_SEC_LEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* RTC section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ABB5ZES3_REG_RTC_SC 0x03 /* RTC Seconds register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ABB5ZES3_REG_RTC_SC_OSC BIT(7) /* Clock integrity status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ABB5ZES3_REG_RTC_MN 0x04 /* RTC Minutes register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ABB5ZES3_REG_RTC_HR 0x05 /* RTC Hours register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ABB5ZES3_REG_RTC_HR_PM BIT(5) /* RTC Hours PM bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ABB5ZES3_REG_RTC_DT 0x06 /* RTC Date register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ABB5ZES3_REG_RTC_DW 0x07 /* RTC Day of the week register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ABB5ZES3_REG_RTC_MO 0x08 /* RTC Month register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ABB5ZES3_REG_RTC_YR 0x09 /* RTC Year register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ABB5ZES3_RTC_SEC_LEN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Alarm section (enable bits are all active low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ABB5ZES3_REG_ALRM_MN 0x0A /* Alarm - minute register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ABB5ZES3_REG_ALRM_MN_AE BIT(7) /* Minute enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ABB5ZES3_REG_ALRM_HR 0x0B /* Alarm - hours register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ABB5ZES3_REG_ALRM_HR_AE BIT(7) /* Hour enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ABB5ZES3_REG_ALRM_DT 0x0C /* Alarm - date register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ABB5ZES3_REG_ALRM_DT_AE BIT(7) /* Date (day of the month) enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ABB5ZES3_REG_ALRM_DW 0x0D /* Alarm - day of the week reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ABB5ZES3_REG_ALRM_DW_AE BIT(7) /* Day of the week enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ABB5ZES3_ALRM_SEC_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Frequency offset section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ABB5ZES3_REG_FREQ_OF 0x0E /* Frequency offset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ABB5ZES3_REG_FREQ_OF_MODE 0x0E /* Offset mode: 2 hours / minute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* CLOCKOUT section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ABB5ZES3_REG_TIM_CLK 0x0F /* Timer & Clockout register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ABB5ZES3_REG_TIM_CLK_TAM BIT(7) /* Permanent/pulsed timer A/int. 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ABB5ZES3_REG_TIM_CLK_TBM BIT(6) /* Permanent/pulsed timer B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ABB5ZES3_REG_TIM_CLK_COF2 BIT(5) /* Clkout Freq bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ABB5ZES3_REG_TIM_CLK_COF1 BIT(4) /* Clkout Freq bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ABB5ZES3_REG_TIM_CLK_COF0 BIT(3) /* Clkout Freq bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ABB5ZES3_REG_TIM_CLK_TAC1 BIT(2) /* Timer A: - 01 : countdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ABB5ZES3_REG_TIM_CLK_TAC0 BIT(1) /* - 10 : timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ABB5ZES3_REG_TIM_CLK_TBC BIT(0) /* Timer B enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Timer A Section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ABB5ZES3_REG_TIMA_CLK 0x10 /* Timer A clock register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ABB5ZES3_REG_TIMA_CLK_TAQ2 BIT(2) /* Freq bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ABB5ZES3_REG_TIMA_CLK_TAQ1 BIT(1) /* Freq bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ABB5ZES3_REG_TIMA_CLK_TAQ0 BIT(0) /* Freq bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ABB5ZES3_REG_TIMA 0x11 /* Timer A register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ABB5ZES3_TIMA_SEC_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Timer B Section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ABB5ZES3_REG_TIMB_CLK 0x12 /* Timer B clock register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ABB5ZES3_REG_TIMB_CLK_TBW2 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ABB5ZES3_REG_TIMB_CLK_TBW1 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ABB5ZES3_REG_TIMB_CLK_TBW0 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ABB5ZES3_REG_TIMB_CLK_TAQ2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ABB5ZES3_REG_TIMB_CLK_TAQ1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ABB5ZES3_REG_TIMB_CLK_TAQ0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ABB5ZES3_REG_TIMB 0x13 /* Timer B register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ABB5ZES3_TIMB_SEC_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ABB5ZES3_MEM_MAP_LEN 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct abb5zes3_rtc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) bool battery_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) bool timer_alarm; /* current alarm is via timer A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Try and match register bits w/ fixed null values to see whether we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * are dealing with an ABB5ZES3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int abb5zes3_i2c_validate_chip(struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u8 regs[ABB5ZES3_MEM_MAP_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const u8 mask[ABB5ZES3_MEM_MAP_LEN] = { 0x00, 0x00, 0x10, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 0x80, 0xc0, 0xc0, 0xf8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 0xe0, 0x00, 0x00, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0x40, 0x78, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 0xf8, 0x00, 0x88, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ret = regmap_bulk_read(regmap, 0, regs, ABB5ZES3_MEM_MAP_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) for (i = 0; i < ABB5ZES3_MEM_MAP_LEN; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (regs[i] & mask[i]) /* check if bits are cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Clear alarm status bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int _abb5zes3_rtc_clear_alarm(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ABB5ZES3_REG_CTRL2_AF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dev_err(dev, "%s: clearing alarm failed (%d)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Enable or disable alarm (i.e. alarm interrupt generation) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int _abb5zes3_rtc_update_alarm(struct device *dev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ABB5ZES3_REG_CTRL1_AIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) enable ? ABB5ZES3_REG_CTRL1_AIE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_err(dev, "%s: writing alarm INT failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Enable or disable timer (watchdog timer A interrupt generation) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int _abb5zes3_rtc_update_timer(struct device *dev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ABB5ZES3_REG_CTRL2_WTAIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) enable ? ABB5ZES3_REG_CTRL2_WTAIE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dev_err(dev, "%s: writing timer INT failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Note: we only read, so regmap inner lock protection is sufficient, i.e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * we do not need driver's main lock protection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int _abb5zes3_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * As we need to read CTRL1 register anyway to access 24/12h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * mode bit, we do a single bulk read of both control and RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * sections (they are consecutive). This also ease indexing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * of register values after bulk read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_CTRL1, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_err(dev, "%s: reading RTC time failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* If clock integrity is not guaranteed, do not return a time value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (regs[ABB5ZES3_REG_RTC_SC] & ABB5ZES3_REG_RTC_SC_OSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) tm->tm_sec = bcd2bin(regs[ABB5ZES3_REG_RTC_SC] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) tm->tm_min = bcd2bin(regs[ABB5ZES3_REG_RTC_MN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (regs[ABB5ZES3_REG_CTRL1] & ABB5ZES3_REG_CTRL1_PM) { /* 12hr mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR] & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (regs[ABB5ZES3_REG_RTC_HR] & ABB5ZES3_REG_RTC_HR_PM) /* PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) tm->tm_hour += 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } else { /* 24hr mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) tm->tm_mday = bcd2bin(regs[ABB5ZES3_REG_RTC_DT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) tm->tm_wday = bcd2bin(regs[ABB5ZES3_REG_RTC_DW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) tm->tm_mon = bcd2bin(regs[ABB5ZES3_REG_RTC_MO]) - 1; /* starts at 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tm->tm_year = bcd2bin(regs[ABB5ZES3_REG_RTC_YR]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int abb5zes3_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) regs[ABB5ZES3_REG_RTC_SC] = bin2bcd(tm->tm_sec); /* MSB=0 clears OSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) regs[ABB5ZES3_REG_RTC_MN] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) regs[ABB5ZES3_REG_RTC_HR] = bin2bcd(tm->tm_hour); /* 24-hour format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) regs[ABB5ZES3_REG_RTC_DT] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) regs[ABB5ZES3_REG_RTC_DW] = bin2bcd(tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) regs[ABB5ZES3_REG_RTC_MO] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) regs[ABB5ZES3_REG_RTC_YR] = bin2bcd(tm->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_RTC_SC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) regs + ABB5ZES3_REG_RTC_SC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ABB5ZES3_RTC_SEC_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Set provided TAQ and Timer A registers (TIMA_CLK and TIMA) based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * given number of seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static inline void sec_to_timer_a(u8 secs, u8 *taq, u8 *timer_a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *taq = ABB5ZES3_REG_TIMA_CLK_TAQ1; /* 1Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) *timer_a = secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Return current number of seconds in Timer A. As we only use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * timer A with a 1Hz freq, this is what we expect to have.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static inline int sec_from_timer_a(u8 *secs, u8 taq, u8 timer_a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (taq != ABB5ZES3_REG_TIMA_CLK_TAQ1) /* 1Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *secs = timer_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * Read alarm currently configured via a watchdog timer using timer A. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * is done by reading current RTC time and adding remaining timer time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int _abb5zes3_rtc_read_timer(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u8 regs[ABB5ZES3_TIMA_SEC_LEN + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned long rtc_secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 timer_secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Instead of doing two separate calls, because they are consecutive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * we grab both clockout register and Timer A section. The latter is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * used to decide if timer A is enabled (as a watchdog timer).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_TIM_CLK, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ABB5ZES3_TIMA_SEC_LEN + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev_err(dev, "%s: reading Timer A section failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* get current time ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* ... convert to seconds ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) rtc_secs = rtc_tm_to_time64(&rtc_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* ... add remaining timer A time ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ret = sec_from_timer_a(&timer_secs, regs[1], regs[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* ... and convert back. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) rtc_time64_to_tm(rtc_secs + timer_secs, alarm_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL2, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL2_WTAIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* Read alarm currently configured via a RTC alarm registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int _abb5zes3_rtc_read_alarm(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned long rtc_secs, alarm_secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u8 regs[ABB5ZES3_ALRM_SEC_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ABB5ZES3_ALRM_SEC_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_err(dev, "%s: reading alarm section failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) alarm_tm->tm_sec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) alarm_tm->tm_min = bcd2bin(regs[0] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) alarm_tm->tm_hour = bcd2bin(regs[1] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) alarm_tm->tm_mday = bcd2bin(regs[2] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) alarm_tm->tm_wday = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * The alarm section does not store year/month. We use the ones in rtc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * section as a basis and increment month and then year if needed to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * alarm after current time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) alarm_tm->tm_year = rtc_tm.tm_year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) alarm_tm->tm_mon = rtc_tm.tm_mon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) rtc_secs = rtc_tm_to_time64(&rtc_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) alarm_secs = rtc_tm_to_time64(alarm_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (alarm_secs < rtc_secs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (alarm_tm->tm_mon == 11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) alarm_tm->tm_mon = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) alarm_tm->tm_year += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) alarm_tm->tm_mon += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL1, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL1_AIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * As the Alarm mechanism supported by the chip is only accurate to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * minute, we use the watchdog timer mechanism provided by timer A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * (up to 256 seconds w/ a second accuracy) for low alarm values (below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * 4 minutes). Otherwise, we use the common alarm mechanism provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * by the chip. In order for that to work, we keep track of currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * configured timer type via 'timer_alarm' flag in our private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int abb5zes3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (data->timer_alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = _abb5zes3_rtc_read_timer(dev, alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = _abb5zes3_rtc_read_alarm(dev, alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * Set alarm using chip alarm mechanism. It is only accurate to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * minute (not the second). The function expects alarm interrupt to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * be disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int _abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct rtc_time *alarm_tm = &alarm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u8 regs[ABB5ZES3_ALRM_SEC_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct rtc_time rtc_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int ret, enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!alarm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned long rtc_secs, alarm_secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * Chip only support alarms up to one month in the future. Let's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * return an error if we get something after that limit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * Comparison is done by incrementing rtc_tm month field by one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * and checking alarm value is still below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (rtc_tm.tm_mon == 11) { /* handle year wrapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) rtc_tm.tm_mon = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) rtc_tm.tm_year += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) rtc_tm.tm_mon += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) rtc_secs = rtc_tm_to_time64(&rtc_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) alarm_secs = rtc_tm_to_time64(alarm_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (alarm_secs > rtc_secs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_err(dev, "%s: alarm maximum is one month in the future (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * Program all alarm registers but DW one. For each register, setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * MSB to 0 enables associated alarm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) regs[0] = bin2bcd(alarm_tm->tm_min) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) regs[1] = bin2bcd(alarm_tm->tm_hour) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) regs[2] = bin2bcd(alarm_tm->tm_mday) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) regs[3] = ABB5ZES3_REG_ALRM_DW_AE; /* do not match day of the week */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ABB5ZES3_ALRM_SEC_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_err(dev, "%s: writing ALARM section failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Record currently configured alarm is not a timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) data->timer_alarm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Enable or disable alarm interrupt generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return _abb5zes3_rtc_update_alarm(dev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * Set alarm using timer watchdog (via timer A) mechanism. The function expects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * timer A interrupt to be disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int _abb5zes3_rtc_set_timer(struct device *dev, struct rtc_wkalrm *alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u8 secs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u8 regs[ABB5ZES3_TIMA_SEC_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u8 mask = ABB5ZES3_REG_TIM_CLK_TAC0 | ABB5ZES3_REG_TIM_CLK_TAC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Program given number of seconds to Timer A registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) sec_to_timer_a(secs, ®s[0], ®s[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_TIMA_CLK, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ABB5ZES3_TIMA_SEC_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev_err(dev, "%s: writing timer section failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* Configure Timer A as a watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_TIM_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mask, ABB5ZES3_REG_TIM_CLK_TAC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dev_err(dev, "%s: failed to update timer\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Record currently configured alarm is a timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) data->timer_alarm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Enable or disable timer interrupt generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return _abb5zes3_rtc_update_timer(dev, alarm->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * The chip has an alarm which is only accurate to the minute. In order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * handle alarms below that limit, we use the watchdog timer function of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * timer A. More precisely, the timer method is used for alarms below 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct rtc_time *alarm_tm = &alarm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned long rtc_secs, alarm_secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct rtc_time rtc_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) rtc_secs = rtc_tm_to_time64(&rtc_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) alarm_secs = rtc_tm_to_time64(alarm_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Let's first disable both the alarm and the timer interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = _abb5zes3_rtc_update_alarm(dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev_err(dev, "%s: unable to disable alarm (%d)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = _abb5zes3_rtc_update_timer(dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dev_err(dev, "%s: unable to disable timer (%d)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) data->timer_alarm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * Let's now configure the alarm; if we are expected to ring in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * more than 240s, then we setup an alarm. Otherwise, a timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if ((alarm_secs > rtc_secs) && ((alarm_secs - rtc_secs) <= 240))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = _abb5zes3_rtc_set_timer(dev, alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) alarm_secs - rtc_secs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ret = _abb5zes3_rtc_set_alarm(dev, alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev_err(dev, "%s: unable to configure alarm (%d)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* Enable or disable battery low irq generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static inline int _abb5zes3_rtc_battery_low_irq_enable(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ABB5ZES3_REG_CTRL3_BLIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) enable ? ABB5ZES3_REG_CTRL3_BLIE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * Check current RTC status and enable/disable what needs to be. Return 0 if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * everything went ok and a negative value upon error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int abb5zes3_rtc_check_setup(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct regmap *regmap = data->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * By default, the devices generates a 32.768KHz signal on IRQ#1 pin. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * is disabled here to prevent polluting the interrupt line and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * uselessly triggering the IRQ handler we install for alarm and battery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * low events. Note: this is done before clearing int. status below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * in this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * We also disable all timers and set timer interrupt to permanent (not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * pulsed).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) mask = (ABB5ZES3_REG_TIM_CLK_TBC | ABB5ZES3_REG_TIM_CLK_TAC0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ABB5ZES3_REG_TIM_CLK_TAC1 | ABB5ZES3_REG_TIM_CLK_COF0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ABB5ZES3_REG_TIM_CLK_COF1 | ABB5ZES3_REG_TIM_CLK_COF2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ABB5ZES3_REG_TIM_CLK_TBM | ABB5ZES3_REG_TIM_CLK_TAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ret = regmap_update_bits(regmap, ABB5ZES3_REG_TIM_CLK, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ABB5ZES3_REG_TIM_CLK_COF0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ABB5ZES3_REG_TIM_CLK_COF1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ABB5ZES3_REG_TIM_CLK_COF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_err(dev, "%s: unable to initialize clkout register (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * Each component of the alarm (MN, HR, DT, DW) can be enabled/disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * individually by clearing/setting MSB of each associated register. So,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * we set all alarm enable bits to disable current alarm setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) mask = (ABB5ZES3_REG_ALRM_MN_AE | ABB5ZES3_REG_ALRM_HR_AE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ABB5ZES3_REG_ALRM_DT_AE | ABB5ZES3_REG_ALRM_DW_AE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dev_err(dev, "%s: unable to disable alarm setting (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Set Control 1 register (RTC enabled, 24hr mode, all int. disabled) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) mask = (ABB5ZES3_REG_CTRL1_CIE | ABB5ZES3_REG_CTRL1_AIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ABB5ZES3_REG_CTRL1_SIE | ABB5ZES3_REG_CTRL1_PM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ABB5ZES3_REG_CTRL1_CAP | ABB5ZES3_REG_CTRL1_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL1, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) dev_err(dev, "%s: unable to initialize CTRL1 register (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * Set Control 2 register (timer int. disabled, alarm status cleared).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * WTAF is read-only and cleared automatically by reading the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) mask = (ABB5ZES3_REG_CTRL2_CTBIE | ABB5ZES3_REG_CTRL2_CTAIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ABB5ZES3_REG_CTRL2_WTAIE | ABB5ZES3_REG_CTRL2_AF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ABB5ZES3_REG_CTRL2_SF | ABB5ZES3_REG_CTRL2_CTBF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ABB5ZES3_REG_CTRL2_CTAF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev_err(dev, "%s: unable to initialize CTRL2 register (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * Enable battery low detection function and battery switchover function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * (standard mode). Disable associated interrupts. Clear battery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * switchover flag but not battery low flag. The latter is checked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * later below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) mask = (ABB5ZES3_REG_CTRL3_PM0 | ABB5ZES3_REG_CTRL3_PM1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ABB5ZES3_REG_CTRL3_PM2 | ABB5ZES3_REG_CTRL3_BLIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ABB5ZES3_REG_CTRL3_BSIE | ABB5ZES3_REG_CTRL3_BSF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dev_err(dev, "%s: unable to initialize CTRL3 register (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Check oscillator integrity flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ret = regmap_read(regmap, ABB5ZES3_REG_RTC_SC, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dev_err(dev, "%s: unable to read osc. integrity flag (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (reg & ABB5ZES3_REG_RTC_SC_OSC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dev_err(dev, "clock integrity not guaranteed. Osc. has stopped or has been interrupted.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_err(dev, "change battery (if not already done) and then set time to reset osc. failure flag.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * Check battery low flag at startup: this allows reporting battery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * is low at startup when IRQ line is not connected. Note: we record
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * current status to avoid reenabling this interrupt later in probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * function if battery is low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ret = regmap_read(regmap, ABB5ZES3_REG_CTRL3, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) dev_err(dev, "%s: unable to read battery low flag (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) data->battery_low = reg & ABB5ZES3_REG_CTRL3_BLF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (data->battery_low) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dev_err(dev, "RTC battery is low; please, consider changing it!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dev_err(dev, "%s: disabling battery low interrupt generation failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static int abb5zes3_rtc_alarm_irq_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (rtc_data->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (rtc_data->timer_alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = _abb5zes3_rtc_update_timer(dev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ret = _abb5zes3_rtc_update_alarm(dev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static irqreturn_t _abb5zes3_rtc_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct i2c_client *client = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct rtc_device *rtc = rtc_data->rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) u8 regs[ABB5ZES3_CTRL_SEC_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) int ret, handled = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ret = regmap_bulk_read(rtc_data->regmap, 0, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ABB5ZES3_CTRL_SEC_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dev_err(dev, "%s: unable to read control section (%d)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * Check battery low detection flag and disable battery low interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * generation if flag is set (interrupt can only be cleared when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * battery is replaced).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (regs[ABB5ZES3_REG_CTRL3] & ABB5ZES3_REG_CTRL3_BLF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) dev_err(dev, "RTC battery is low; please change it!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) _abb5zes3_rtc_battery_low_irq_enable(rtc_data->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* Check alarm flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_AF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dev_dbg(dev, "RTC alarm!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* Acknowledge and disable the alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) _abb5zes3_rtc_clear_alarm(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) _abb5zes3_rtc_update_alarm(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Check watchdog Timer A flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_WTAF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dev_dbg(dev, "RTC timer!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * Acknowledge and disable the alarm. Note: WTAF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * flag had been cleared when reading CTRL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) _abb5zes3_rtc_update_timer(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) rtc_data->timer_alarm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static const struct rtc_class_ops rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .read_time = _abb5zes3_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .set_time = abb5zes3_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .read_alarm = abb5zes3_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .set_alarm = abb5zes3_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .alarm_irq_enable = abb5zes3_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static const struct regmap_config abb5zes3_rtc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static int abb5zes3_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct abb5zes3_rtc_data *data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) I2C_FUNC_SMBUS_BYTE_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) I2C_FUNC_SMBUS_I2C_BLOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) regmap = devm_regmap_init_i2c(client, &abb5zes3_rtc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ret = PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dev_err(dev, "%s: regmap allocation failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ret = abb5zes3_i2c_validate_chip(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) data->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) dev_set_drvdata(dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ret = abb5zes3_rtc_check_setup(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) data->rtc = devm_rtc_allocate_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ret = PTR_ERR_OR_ZERO(data->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dev_err(dev, "%s: unable to allocate RTC device (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ret = devm_request_threaded_irq(dev, client->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) _abb5zes3_rtc_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) IRQF_SHARED | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) DRV_NAME, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) device_init_wakeup(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) data->irq = client->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) dev_dbg(dev, "%s: irq %d used by RTC\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_err(dev, "%s: irq %d unavailable (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) __func__, client->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) data->rtc->ops = &rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) data->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) data->rtc->range_max = RTC_TIMESTAMP_END_2099;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* Enable battery low detection interrupt if battery not already low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (!data->battery_low && data->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dev_err(dev, "%s: enabling battery low interrupt generation failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ret = rtc_register_device(data->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (ret && data->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) device_init_wakeup(dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static int abb5zes3_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return enable_irq_wake(rtc_data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static int abb5zes3_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return disable_irq_wake(rtc_data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static SIMPLE_DEV_PM_OPS(abb5zes3_rtc_pm_ops, abb5zes3_rtc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) abb5zes3_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static const struct of_device_id abb5zes3_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) { .compatible = "abracon,abb5zes3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) MODULE_DEVICE_TABLE(of, abb5zes3_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static const struct i2c_device_id abb5zes3_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) { "abb5zes3", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) MODULE_DEVICE_TABLE(i2c, abb5zes3_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static struct i2c_driver abb5zes3_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .pm = &abb5zes3_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .of_match_table = of_match_ptr(abb5zes3_dt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .probe = abb5zes3_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .id_table = abb5zes3_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) module_i2c_driver(abb5zes3_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) MODULE_AUTHOR("Arnaud EBALARD <arno@natisbad.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) MODULE_DESCRIPTION("Abracon AB-RTCMC-32.768kHz-B5ZE-S3 RTC/Alarm driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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