^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016, Linaro Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/rpmsg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/idr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/circ_buf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/soc/qcom/smem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/rpmsg/qcom_glink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "qcom_glink_native.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FIFO_FULL_RESERVE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FIFO_ALIGNMENT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TX_BLOCKED_CMD_RESERVE 8 /* size of struct read_notif_request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR 478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SMEM_GLINK_NATIVE_XPRT_FIFO_0 479
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SMEM_GLINK_NATIVE_XPRT_FIFO_1 480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct glink_smem_pipe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct qcom_glink_pipe native;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) __le32 *tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) __le32 *head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void *fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int remote_pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define to_smem_pipe(p) container_of(p, struct glink_smem_pipe, native)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static size_t glink_smem_rx_avail(struct qcom_glink_pipe *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct glink_smem_pipe *pipe = to_smem_pipe(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void *fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (!pipe->fifo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) fifo = qcom_smem_get(pipe->remote_pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SMEM_GLINK_NATIVE_XPRT_FIFO_1, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (IS_ERR(fifo)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pr_err("failed to acquire RX fifo handle: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PTR_ERR(fifo));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) pipe->fifo = fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pipe->native.length = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) head = le32_to_cpu(*pipe->head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) tail = le32_to_cpu(*pipe->tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (head < tail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return pipe->native.length - tail + head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return head - tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void glink_smem_rx_peak(struct qcom_glink_pipe *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void *data, unsigned int offset, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct glink_smem_pipe *pipe = to_smem_pipe(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) tail = le32_to_cpu(*pipe->tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) tail += offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (tail >= pipe->native.length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) tail -= pipe->native.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) len = min_t(size_t, count, pipe->native.length - tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) memcpy_fromio(data, pipe->fifo + tail, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (len != count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) memcpy_fromio(data + len, pipe->fifo, (count - len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void glink_smem_rx_advance(struct qcom_glink_pipe *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct glink_smem_pipe *pipe = to_smem_pipe(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) tail = le32_to_cpu(*pipe->tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) tail += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (tail >= pipe->native.length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) tail -= pipe->native.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *pipe->tail = cpu_to_le32(tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static size_t glink_smem_tx_avail(struct qcom_glink_pipe *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct glink_smem_pipe *pipe = to_smem_pipe(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) head = le32_to_cpu(*pipe->head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) tail = le32_to_cpu(*pipe->tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (tail <= head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) avail = pipe->native.length - head + tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) avail = tail - head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (avail < (FIFO_FULL_RESERVE + TX_BLOCKED_CMD_RESERVE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) avail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) avail -= FIFO_FULL_RESERVE + TX_BLOCKED_CMD_RESERVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static unsigned int glink_smem_tx_write_one(struct glink_smem_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const void *data, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) len = min_t(size_t, count, pipe->native.length - head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) memcpy(pipe->fifo + head, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (len != count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) memcpy(pipe->fifo, data + len, count - len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) head += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (head >= pipe->native.length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) head -= pipe->native.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void glink_smem_tx_write(struct qcom_glink_pipe *glink_pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) const void *hdr, size_t hlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const void *data, size_t dlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct glink_smem_pipe *pipe = to_smem_pipe(glink_pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) head = le32_to_cpu(*pipe->head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) head = glink_smem_tx_write_one(pipe, head, hdr, hlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) head = glink_smem_tx_write_one(pipe, head, data, dlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Ensure head is always aligned to 8 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) head = ALIGN(head, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (head >= pipe->native.length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) head -= pipe->native.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Ensure ordering of fifo and head update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *pipe->head = cpu_to_le32(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void qcom_glink_smem_release(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct qcom_glink *qcom_glink_smem_register(struct device *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct glink_smem_pipe *rx_pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct glink_smem_pipe *tx_pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct qcom_glink *glink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 remote_pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __le32 *descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dev = kzalloc(sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev->parent = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev->of_node = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev->release = qcom_glink_smem_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev_set_name(dev, "%s:%pOFn", dev_name(parent->parent), node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = device_register(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pr_err("failed to register glink edge\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) put_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ret = of_property_read_u32(dev->of_node, "qcom,remote-pid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) &remote_pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dev_err(dev, "failed to parse qcom,remote-pid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) goto err_put_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) rx_pipe = devm_kzalloc(dev, sizeof(*rx_pipe), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) tx_pipe = devm_kzalloc(dev, sizeof(*tx_pipe), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!rx_pipe || !tx_pipe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) goto err_put_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = qcom_smem_alloc(remote_pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret && ret != -EEXIST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_err(dev, "failed to allocate glink descriptors\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) goto err_put_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) descs = qcom_smem_get(remote_pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (IS_ERR(descs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dev_err(dev, "failed to acquire xprt descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = PTR_ERR(descs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) goto err_put_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (size != 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_err(dev, "glink descriptor of invalid size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) goto err_put_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tx_pipe->tail = &descs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) tx_pipe->head = &descs[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) rx_pipe->tail = &descs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) rx_pipe->head = &descs[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = qcom_smem_alloc(remote_pid, SMEM_GLINK_NATIVE_XPRT_FIFO_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) SZ_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ret && ret != -EEXIST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_err(dev, "failed to allocate TX fifo\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) goto err_put_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) tx_pipe->fifo = qcom_smem_get(remote_pid, SMEM_GLINK_NATIVE_XPRT_FIFO_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) &tx_pipe->native.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (IS_ERR(tx_pipe->fifo)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_err(dev, "failed to acquire TX fifo\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = PTR_ERR(tx_pipe->fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) goto err_put_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) rx_pipe->native.avail = glink_smem_rx_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) rx_pipe->native.peak = glink_smem_rx_peak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) rx_pipe->native.advance = glink_smem_rx_advance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) rx_pipe->remote_pid = remote_pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) tx_pipe->native.avail = glink_smem_tx_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) tx_pipe->native.write = glink_smem_tx_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) tx_pipe->remote_pid = remote_pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) *rx_pipe->tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *tx_pipe->head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) glink = qcom_glink_native_probe(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) GLINK_FEATURE_INTENT_REUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) &rx_pipe->native, &tx_pipe->native,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (IS_ERR(glink)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = PTR_ERR(glink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) goto err_put_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return glink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) err_put_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) device_unregister(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) EXPORT_SYMBOL_GPL(qcom_glink_smem_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) void qcom_glink_smem_unregister(struct qcom_glink *glink)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) qcom_glink_native_remove(glink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) qcom_glink_native_unregister(glink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) EXPORT_SYMBOL_GPL(qcom_glink_smem_unregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_DESCRIPTION("Qualcomm GLINK SMEM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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