^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) Rockchip Electronics Co.Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Felix Zeng <felix.zeng@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "rknpu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef FPGA_PLATFORM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static inline struct reset_control *rknpu_reset_control_get(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct reset_control *rst = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) rst = devm_reset_control_get(dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) if (IS_ERR(rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) LOG_DEV_ERROR(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) "failed to get rknpu reset control: %s, %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) name, PTR_ERR(rst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) return rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int rknpu_reset_get(struct rknpu_device *rknpu_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifndef FPGA_PLATFORM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct reset_control *srst_a = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct reset_control *srst_h = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) for (i = 0; i < rknpu_dev->config->num_resets; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) srst_a = rknpu_reset_control_get(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) rknpu_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) rknpu_dev->config->resets[i].srst_a_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (IS_ERR(srst_a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return PTR_ERR(srst_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) rknpu_dev->srst_a[i] = srst_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) srst_h = rknpu_reset_control_get(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) rknpu_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) rknpu_dev->config->resets[i].srst_h_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (IS_ERR(srst_h))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return PTR_ERR(srst_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) rknpu_dev->srst_h[i] = srst_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #ifndef FPGA_PLATFORM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int rknpu_reset_assert(struct reset_control *rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (!rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ret = reset_control_assert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) LOG_ERROR("failed to assert rknpu reset: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int rknpu_reset_deassert(struct reset_control *rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ret = reset_control_deassert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) LOG_ERROR("failed to deassert rknpu reset: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int rknpu_soft_reset(struct rknpu_device *rknpu_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #ifndef FPGA_PLATFORM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct iommu_domain *domain = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct rknpu_subcore_data *subcore_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int ret = -EINVAL, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (rknpu_dev->bypass_soft_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) LOG_WARN("bypass soft reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!mutex_trylock(&rknpu_dev->reset_lock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) rknpu_dev->soft_reseting = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) for (i = 0; i < rknpu_dev->config->num_irqs; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) subcore_data = &rknpu_dev->subcore_datas[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) wake_up(&subcore_data->job_done_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) LOG_INFO("soft reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) for (i = 0; i < rknpu_dev->config->num_resets; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = rknpu_reset_assert(rknpu_dev->srst_a[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ret |= rknpu_reset_assert(rknpu_dev->srst_h[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret |= rknpu_reset_deassert(rknpu_dev->srst_a[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret |= rknpu_reset_deassert(rknpu_dev->srst_h[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) LOG_DEV_ERROR(rknpu_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "failed to soft reset for rknpu: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mutex_unlock(&rknpu_dev->reset_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (rknpu_dev->iommu_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) domain = iommu_get_domain_for_dev(rknpu_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) iommu_detach_device(domain, rknpu_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) iommu_attach_device(domain, rknpu_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) rknpu_dev->soft_reseting = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mutex_unlock(&rknpu_dev->reset_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags