^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef _SFC_NOR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define _SFC_NOR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "sfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define NOR_PAGE_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define NOR_BLOCK_SIZE (64 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define NOR_SECS_BLK (NOR_BLOCK_SIZE / 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define NOR_SECS_PAGE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define FEA_READ_STATUE_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define FEA_STATUE_MODE1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define FEA_STATUE_MODE2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FEA_4BIT_READ BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define FEA_4BIT_PROG BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FEA_4BYTE_ADDR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FEA_4BYTE_ADDR_MODE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*Command Set*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CMD_READ_JEDECID (0x9F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CMD_READ_DATA (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CMD_READ_STATUS (0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CMD_WRITE_STATUS (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CMD_PAGE_PROG (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CMD_SECTOR_ERASE (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CMD_BLK64K_ERASE (0xD8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CMD_BLK32K_ERASE (0x52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CMD_CHIP_ERASE (0xC7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CMD_WRITE_EN (0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CMD_WRITE_DIS (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CMD_PAGE_READ (0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CMD_PAGE_FASTREAD4B (0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CMD_GET_FEATURE (0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CMD_SET_FEATURE (0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CMD_PROG_LOAD (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CMD_PROG_EXEC (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CMD_BLOCK_ERASE (0xD8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CMD_READ_DATA_X2 (0x3B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CMD_READ_DATA_X4 (0x6B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CMD_PROG_LOAD_X4 (0x32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CMD_READ_STATUS2 (0x35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CMD_READ_STATUS3 (0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CMD_WRITE_STATUS2 (0x31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CMD_WRITE_STATUS3 (0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* X1 cmd, X1 addr, X1 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CMD_FAST_READ_X1 (0x0B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* X1 cmd, X1 addr, X2 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CMD_FAST_READ_X2 (0x3B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CMD_FAST_READ_X4 (0x6B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CMD_FAST_4READ_X4 (0x6C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* X1 cmd, X4 addr, X4 data SUPPORT EON GD MARCONIX WINBOND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CMD_FAST_READ_A4 (0xEB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* X1 cmd, X1 addr, X4 data, SUPPORT GD WINBOND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CMD_PAGE_PROG_X4 (0x32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* X1 cmd, X4 addr, X4 data, SUPPORT MARCONIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CMD_PAGE_PROG_A4 (0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* X1 cmd, X4 addr, X4 data, SUPPORT MARCONIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CMD_PAGE_PROG_4PP (0x3E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CMD_RESET_NAND (0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CMD_ENTER_4BYTE_MODE (0xB7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CMD_EXIT_4BYTE_MODE (0xE9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CMD_ENABLE_RESER (0x66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CMD_RESET_DEVICE (0x99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CMD_READ_PARAMETER (0x5A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) enum NOR_ERASE_TYPE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ERASE_SECTOR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ERASE_BLOCK64K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ERASE_CHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) enum SNOR_IO_MODE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) IO_MODE_SPI = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) IO_MODE_QPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum SNOR_READ_MODE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) READ_MODE_NOMAL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) READ_MODE_FAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum SNOR_ADDR_MODE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ADDR_MODE_3BYTE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ADDR_MODE_4BYTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) typedef int (*SNOR_WRITE_STATUS)(u32 reg_index, u8 status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct SFNOR_DEV {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 capacity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 manufacturer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 mem_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u16 page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 blk_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u8 read_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 prog_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 sec_erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 blk_erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 QE_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) enum SNOR_READ_MODE read_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) enum SNOR_ADDR_MODE addr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) enum SNOR_IO_MODE io_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enum SFC_DATA_LINES read_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enum SFC_DATA_LINES prog_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum SFC_DATA_LINES prog_addr_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SNOR_WRITE_STATUS write_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 max_iosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct flash_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 sector_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u8 read_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 prog_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 read_cmd_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u8 prog_cmd_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 sector_erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 block_erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 density; /* (1 << density) sectors*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u8 QE_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u8 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* flash table packet for easy boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SNOR_INFO_PACKET_ID 0x464E494E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SNOR_INFO_PACKET_HEAD_LEN 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SNOR_INFO_PACKET_SPI_MODE_RATE_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct snor_info_packet {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 head_hash; /*hash for head, check by bootrom.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u16 head_len; /*320 - 16 bytes*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u16 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u8 read_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 prog_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 read_cmd_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u8 prog_cmd_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u8 sector_erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u8 block_erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 QE_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 spi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int snor_init(struct SFNOR_DEV *p_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 snor_get_capacity(struct SFNOR_DEV *p_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int snor_erase(struct SFNOR_DEV *p_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) enum NOR_ERASE_TYPE erase_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int snor_read_id(u8 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int snor_prog_page(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int snor_read_data(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int snor_reset_device(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int snor_disable_QE(struct SFNOR_DEV *p_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int snor_reinit_from_table_packet(struct SFNOR_DEV *p_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct snor_info_packet *packet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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