^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef _SFC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define _SFC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define SFC_VER_3 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define SFC_VER_4 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define SFC_VER_5 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SFC_EN_INT (0) /* enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SFC_EN_DMA (1) /* enable dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SFC_FIFO_DEPTH (0x10) /* 16 words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* FIFO watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SFC_RX_WMARK (SFC_FIFO_DEPTH) /* RX watermark level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SFC_TX_WMARK (SFC_FIFO_DEPTH) /* TX watermark level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SFC_RX_WMARK_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SFC_TX_WMARK_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* return value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SFC_OK (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SFC_ERROR (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SFC_PARAM_ERR (-2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SFC_TX_TIMEOUT (-3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SFC_RX_TIMEOUT (-4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SFC_WAIT_TIMEOUT (-5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SFC_BUSY_TIMEOUT (-6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SFC_ECC_FAIL (-7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SFC_PROG_FAIL (-8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SFC_ERASE_FAIL (-9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* SFC_CMD Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SFC_ADDR_0BITS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SFC_ADDR_24BITS (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SFC_ADDR_32BITS (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SFC_ADDR_XBITS (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SFC_WRITE (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SFC_READ (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* SFC_CTRL Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SFC_1BITS_LINE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SFC_2BITS_LINE (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SFC_4BITS_LINE (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SFC_ENABLE_DMA BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define sfc_delay(us) udelay(us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DMA_INT BIT(7) /* dma interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NSPIERR_INT BIT(6) /* Nspi error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AHBERR_INT BIT(5) /* Ahb bus error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FINISH_INT BIT(4) /* Transfer finish interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TXEMPTY_INT BIT(3) /* Tx fifo empty interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TXOF_INT BIT(2) /* Tx fifo overflow interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RXUF_INT BIT(1) /* Rx fifo underflow interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RXFULL_INT BIT(0) /* Rx fifo full interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* SFC_FSR Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SFC_RXFULL BIT(3) /* rx fifo full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SFC_RXEMPTY BIT(2) /* rx fifo empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SFC_TXEMPTY BIT(1) /* tx fifo empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SFC_TXFULL BIT(0) /* tx fifo full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* SFC_RCVR Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SFC_RESET BIT(0) /* controller reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* SFC_DLL_CTRL Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SCLK_SMP_SEL_EN BIT(15) /* SCLK Sampling Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SCLK_SMP_SEL_MAX_V4 0x1FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SCLK_SMP_SEL_MAX_V5 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SFC_DLL_TRANING_STEP 10 /* Training step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SFC_DLL_TRANING_VALID_WINDOW 80 /* Valid DLL winbow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* SFC_SR Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* sfc busy flag. When busy, don't try to set the control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SFC_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* SFC_DMA_TRIGGER Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Dma start trigger signal. Auto cleared after write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SFC_DMA_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SFC_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SFC_IMR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SFC_ICLR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SFC_FTLR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SFC_RCVR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SFC_AX 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SFC_ABIT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SFC_MASKISR 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SFC_FSR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SFC_SR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SFC_RAWISR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SFC_VER 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SFC_QOP 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SFC_DLL_CTRL0 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SFC_DMA_TRIGGER 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SFC_DMA_ADDR 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SFC_LEN_CTRL 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SFC_LEN_EXT 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SFC_CMD 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SFC_ADDR 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SFC_DATA 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) union SFCFSR_DATA {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned txempty : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned txfull : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned rxempty : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned rxfull : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned reserved7_4 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned txlevel : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned reserved15_13 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned rxlevel : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned reserved31_21 : 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) } b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Manufactory ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MID_WINBOND 0xEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MID_GIGADEV 0xC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MID_MICRON 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MID_MACRONIX 0xC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MID_SPANSION 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MID_EON 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MID_ST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MID_XTX 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MID_PUYA 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MID_XMC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MID_DOSILICON 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MID_ZBIT 0x5E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*------------------------------ Global Typedefs -----------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) enum SFC_DATA_LINES {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DATA_LINES_X1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DATA_LINES_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DATA_LINES_X4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) union SFCCTRL_DATA {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* raw register data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* spi mode select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned mode : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * Shift in phase selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * 0: shift in the flash data at posedge sclk_out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * 1: shift in the flash data at negedge sclk_out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned sps : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned reserved3_2 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* sclk_idle_level_cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned scic : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Cmd bits number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned cmdlines : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Address bits number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned addrlines : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Data bits number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned datalines : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* this bit is not exit in regiseter, just use for code param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned enbledma : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned reserved15 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned addrbits : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned reserved31_21 : 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) } b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) union SFCCMD_DATA {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* raw register data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Command that will send to Serial Flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned cmd : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Dummy bits number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned dummybits : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* 0: read, 1: write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned rw : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Continuous read mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned readmode : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Address bits number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned addrbits : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Transferred bytes number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned datasize : 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned cs : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) } b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct rk_sfc_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) union SFCCMD_DATA sfcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) union SFCCTRL_DATA sfctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IDB_BLOCK_TAG_ID 0xFCDC8C3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct id_block_tag {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u16 boot_img_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 reserved1[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 dev_param[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 reserved2[506 - 56];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u16 data_img_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u16 boot_img_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 reserved3[512 - 510];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int sfc_init(void __iomem *reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int sfc_request(struct rk_sfc_op *op, u32 addr, void *data, u32 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u16 sfc_get_version(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) void sfc_clean_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 sfc_get_max_iosize(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) void sfc_set_delay_lines(u16 cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void sfc_handle_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned long rksfc_dma_map_single(unsigned long ptr, int size, int dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) void rksfc_dma_unmap_single(unsigned long ptr, int size, int dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void rksfc_irq_flag_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) void rksfc_wait_for_irq_completed(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 sfc_get_max_dll_cells(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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