Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "sfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "rkflash_api.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "rkflash_blk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define RKSFC_VERSION_AND_DATE		"rksfc_base v1.1 2016-01-08"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define RKSFC_CLK_MAX_RATE		(150 * 1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define RKSFC_DLL_THRESHOLD_RATE	(50 * 1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) struct rksfc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	void __iomem	*reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	int	irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	int	clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct clk	*clk;		/* sfc clk*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct clk	*ahb_clk;	/* ahb clk gate*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u16	dll_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static struct rksfc_info g_sfc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static struct device *g_sfc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static struct completion sfc_irq_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) unsigned long rksfc_dma_map_single(unsigned long ptr, int size, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	return dma_map_single(g_sfc_dev, (void *)ptr, size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		, dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) void rksfc_dma_unmap_single(unsigned long ptr, int size, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	dma_unmap_single(g_sfc_dev, (dma_addr_t)ptr, size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		, dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static irqreturn_t rksfc_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	sfc_clean_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	complete(&sfc_irq_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) void rksfc_irq_flag_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	init_completion(&sfc_irq_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) void rksfc_wait_for_irq_completed(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	wait_for_completion_timeout(&sfc_irq_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 				    msecs_to_jiffies(10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static int rksfc_irq_config(int mode, void *pfun)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	int irq = g_sfc_info.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	if (mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		ret = request_irq(irq, pfun, 0, "rksfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 				  g_sfc_info.reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		free_irq(irq,  NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static int rksfc_irq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	init_completion(&sfc_irq_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	rksfc_irq_config(1, rksfc_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static int rksfc_irq_deinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	rksfc_irq_config(0, rksfc_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static void rksfc_delay_lines_tuning(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	u8 id[3], id_temp[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct rk_sfc_op op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u16 cell_max = (u16)sfc_get_max_dll_cells();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u16 right, left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	u16 step = SFC_DLL_TRANING_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	bool dll_valid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	op.sfcmd.d32 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	op.sfcmd.b.cmd = 0x9F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	op.sfctrl.d32 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	clk_set_rate(g_sfc_info.clk, RKSFC_DLL_THRESHOLD_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	sfc_request(&op, 0, id, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if ((0xFF == id[0] && 0xFF == id[1]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	    (0x00 == id[0] && 0x00 == id[1])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		dev_dbg(g_sfc_dev, "no dev, dll by pass\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		clk_set_rate(g_sfc_info.clk, g_sfc_info.clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	clk_set_rate(g_sfc_info.clk, g_sfc_info.clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	for (right = 0; right <= cell_max; right += step) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		sfc_set_delay_lines(right);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		sfc_request(&op, 0, id_temp, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		dev_dbg(g_sfc_dev, "dll read flash id:%x %x %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			id_temp[0], id_temp[1], id_temp[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		ret = memcmp(&id, &id_temp, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		if (dll_valid && ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			right -= step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		if (!dll_valid && !ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			left = right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			dll_valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		/* Add cell_max to loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		if (right == cell_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		if (right + step > cell_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			right = cell_max - step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (dll_valid && (right - left) >= SFC_DLL_TRANING_VALID_WINDOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		if (left == 0 && right < cell_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			g_sfc_info.dll_cells = left + (right - left) * 2 / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			g_sfc_info.dll_cells = left + (right - left) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		g_sfc_info.dll_cells = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (g_sfc_info.dll_cells) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		dev_dbg(g_sfc_dev, "%d %d %d dll training success in %dMHz max_cells=%u sfc_ver=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			left, right, g_sfc_info.dll_cells, g_sfc_info.clk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			sfc_get_max_dll_cells(), sfc_get_version());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		sfc_set_delay_lines((u16)g_sfc_info.dll_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		dev_err(g_sfc_dev, "%d %d dll training failed in %dMHz, reduce the frequency\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			left, right, g_sfc_info.clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		sfc_set_delay_lines(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		clk_set_rate(g_sfc_info.clk, RKSFC_DLL_THRESHOLD_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		g_sfc_info.clk_rate = clk_get_rate(g_sfc_info.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int rksfc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct resource	*mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	void __iomem	*membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	int dev_result = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	g_sfc_dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	membase = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (!membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		dev_err(&pdev->dev, "no reg resource?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		dev_err(&pdev->dev, "no irq resource?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	g_sfc_info.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	g_sfc_info.reg_base = membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	g_sfc_info.ahb_clk = devm_clk_get(&pdev->dev, "hclk_sfc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	g_sfc_info.clk = devm_clk_get(&pdev->dev, "clk_sfc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (unlikely(IS_ERR(g_sfc_info.clk)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	    unlikely(IS_ERR(g_sfc_info.ahb_clk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		dev_err(&pdev->dev, "%s get clk error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	clk_prepare_enable(g_sfc_info.ahb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	g_sfc_info.clk_rate = clk_get_rate(g_sfc_info.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (g_sfc_info.clk_rate > RKSFC_CLK_MAX_RATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		clk_set_rate(g_sfc_info.clk, RKSFC_CLK_MAX_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		g_sfc_info.clk_rate = clk_get_rate(g_sfc_info.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	clk_prepare_enable(g_sfc_info.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		 "%s clk rate = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		 __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		 g_sfc_info.clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	rksfc_irq_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (readl_poll_timeout(membase + SFC_SR, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			       !(status & SFC_BUSY), 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			       500 * USEC_PER_MSEC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		dev_err(g_sfc_dev, "Wait for SFC idle timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	sfc_init(g_sfc_info.reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (sfc_get_version() >= SFC_VER_4 && g_sfc_info.clk_rate > RKSFC_DLL_THRESHOLD_RATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		rksfc_delay_lines_tuning();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	else if (sfc_get_version() >= SFC_VER_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		sfc_set_delay_lines(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #ifdef CONFIG_RK_SFC_NOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	dev_result = rkflash_dev_init(g_sfc_info.reg_base, FLASH_TYPE_SFC_NOR, &sfc_nor_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #ifdef CONFIG_RK_SFC_NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (dev_result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		dev_result = rkflash_dev_init(g_sfc_info.reg_base, FLASH_TYPE_SFC_NAND, &sfc_nand_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (dev_result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		return dev_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	return dma_set_mask(g_sfc_dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int __maybe_unused rksfc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	return rkflash_dev_suspend();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int __maybe_unused rksfc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (g_sfc_info.dll_cells)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		sfc_set_delay_lines(g_sfc_info.dll_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	return rkflash_dev_resume(g_sfc_info.reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static SIMPLE_DEV_PM_OPS(rksfc_pmops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			 rksfc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			 rksfc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void rksfc_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	rkflash_dev_shutdown();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct of_device_id of_rksfc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	{.compatible = "rockchip,sfc"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct platform_driver rksfc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.probe		= rksfc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.shutdown	= rksfc_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.name	= "rksfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		.of_match_table	= of_rksfc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		.pm		= &rksfc_pmops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static void __exit rksfc_driver_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	rkflash_dev_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	rksfc_irq_deinit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	platform_driver_unregister(&rksfc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int __init rksfc_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	pr_err("%s\n", RKSFC_VERSION_AND_DATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	ret = platform_driver_register(&rksfc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) module_init(rksfc_driver_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) module_exit(rksfc_driver_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MODULE_ALIAS("rksfc");