^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "nandc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "rkflash_api.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "rkflash_blk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RKNANDC_VERSION_AND_DATE "rknandc_base v1.1 2017-01-11"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RKNANDC_CLK_SET_RATE (150 * 1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct rknandc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct clk *clk; /* controller's clk*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct clk *ahb_clk; /* ahb clk gate*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct clk *g_clk; /* clk_src_en gate*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct rknandc_info g_nandc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct device *g_nandc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static struct completion nandc_irq_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long rknandc_dma_map_single(unsigned long ptr, int size, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return dma_map_single(g_nandc_dev, (void *)ptr, size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) , dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void rknandc_dma_unmap_single(unsigned long ptr, int size, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) dma_unmap_single(g_nandc_dev, (dma_addr_t)ptr, size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) , dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static irqreturn_t rknandc_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) nandc_clean_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) complete(&nandc_irq_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int rknandc_irq_config(int mode, void *pfun)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int irq = g_nandc_info.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ret = request_irq(irq, pfun, 0, "rknandc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) g_nandc_info.reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) free_irq(irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int rknandc_irq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) init_completion(&nandc_irq_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) rknandc_irq_config(1, rknandc_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int rknandc_irq_deinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) rknandc_irq_config(0, rknandc_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int rknandc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) g_nandc_dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) membase = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dev_err(&pdev->dev, "no reg resource?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dev_err(&pdev->dev, "no irq resource?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) g_nandc_info.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) g_nandc_info.reg_base = membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) g_nandc_info.ahb_clk = devm_clk_get(&pdev->dev, "hclk_nandc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) g_nandc_info.clk = devm_clk_get(&pdev->dev, "clk_nandc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) g_nandc_info.g_clk = devm_clk_get(&pdev->dev, "g_clk_nandc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (unlikely(IS_ERR(g_nandc_info.clk)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unlikely(IS_ERR(g_nandc_info.ahb_clk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) dev_err(&pdev->dev, "%s get clk error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clk_prepare_enable(g_nandc_info.ahb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!(IS_ERR(g_nandc_info.g_clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) clk_prepare_enable(g_nandc_info.g_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clk_set_rate(g_nandc_info.clk, RKNANDC_CLK_SET_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) g_nandc_info.clk_rate = clk_get_rate(g_nandc_info.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) clk_prepare_enable(g_nandc_info.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "%s clk rate = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) g_nandc_info.clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) rknandc_irq_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = rkflash_dev_init(g_nandc_info.reg_base, FLASH_TYPE_NANDC_NAND, &nandc_nand_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return dma_set_mask(g_nandc_dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int __maybe_unused rknandc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return rkflash_dev_suspend();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int __maybe_unused rknandc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return rkflash_dev_resume(g_nandc_info.reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static SIMPLE_DEV_PM_OPS(rknandc_pmops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) rknandc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) rknandc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void rknandc_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) rkflash_dev_shutdown();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const struct of_device_id of_rknandc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {.compatible = "rockchip,rk-nandc"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {.compatible = "rockchip,nandc"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct platform_driver rknandc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .probe = rknandc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .shutdown = rknandc_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .name = "rknandc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .of_match_table = of_rknandc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .pm = &rknandc_pmops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void __exit rknandc_driver_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) rkflash_dev_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) rknandc_irq_deinit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) platform_driver_unregister(&rknandc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int __init rknandc_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pr_err("%s\n", RKNANDC_VERSION_AND_DATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = platform_driver_register(&rknandc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) module_init(rknandc_driver_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) module_exit(rknandc_driver_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MODULE_ALIAS("rknandc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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