Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #ifndef __NAND_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define __NAND_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define nandc_writel(v, offs)	writel((v), (offs) + nandc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define nandc_readl(offs)	readl((offs) + nandc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define NANDC_READ	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define NANDC_WRITE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define RK3326_NANDC_VER	0x56393030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* INT ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) enum NANDC_IRQ_NUM_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	NC_IRQ_DMA = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	NC_IRQ_FRDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	NC_IRQ_BCHERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	NC_IRQ_BCHFAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	NC_IRQ_LLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) enum ENUM_NANDC_BCH_CFG {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	NC_BCH_70 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	NC_BCH_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	NC_BCH_40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	NC_BCH_60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) union FM_CTL_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		unsigned cs : 8;		/* bits[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		unsigned wp : 1;		/* bits[8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		unsigned rdy : 1;		/* bits[9] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		unsigned fifo_empty : 1;	/* bits[10] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		unsigned reserved11 : 1;	/* bits[11] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		unsigned dwidth : 1;		/* bits[12] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		unsigned tm : 1;		/* bits[13] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		unsigned onficlk_en : 1;	/* bits[14] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		unsigned toggle_en : 1;		/* bits[15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		unsigned flash_abort_en : 1;	/* bits[16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		unsigned flash_abort_clear : 1;	/* bits[17] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		unsigned reserved18_23 : 6;	/* bits[18:23] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		unsigned read_delay : 3;	/* bits[24:26] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		unsigned reserved27_31 : 5;	/* bits[27:31] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	} V6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		unsigned cs : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		unsigned wp : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		unsigned frdy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		unsigned fifo_empth_flash : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		unsigned reserved11_12 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		unsigned tm : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		unsigned syn_clken : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		unsigned syn_mode : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		unsigned flash_abort_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		unsigned flash_abort_clear : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		unsigned sif_read_delay : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		unsigned io_mux : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		unsigned reserved24_31 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	} V9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) union FM_WAIT_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		unsigned csrw : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		unsigned rwpw : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		unsigned rdy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		unsigned rwcs : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		unsigned reserved18_23 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		unsigned fmw_dly : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		unsigned fmw_dly_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		unsigned reserved31_31 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	} V6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		unsigned rwcs : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		unsigned rwpw : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		unsigned hard_rdy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		unsigned csrw : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		unsigned wait_frdy_dly : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		unsigned reserved23_23 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		unsigned fmw_dly : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		unsigned fmw_dly_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		unsigned reserved31_31 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	} V9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) union FL_CTL_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		unsigned rst : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		unsigned rdn : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		unsigned start : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		unsigned dma : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		unsigned st_addr : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		unsigned tr_count : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		unsigned rdy_ignore : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		/* unsigned int_clr : 1; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		/* unsigned int_en : 1; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		unsigned reserved8_9 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		unsigned cor_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		unsigned lba_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		unsigned spare_size : 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		unsigned reserved19 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		unsigned tr_rdy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		unsigned page_size : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		unsigned page_num : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		unsigned low_power : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		unsigned async_tog_mix : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		unsigned reserved30_31 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	} V6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		unsigned flash_rst : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		unsigned flash_rdn : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		unsigned flash_st : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		unsigned bypass : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		unsigned st_addr : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		unsigned tr_count : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		unsigned flash_st_mod : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		unsigned not_tran_data : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		unsigned tran_seed : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		unsigned cor_able : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		unsigned lba_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		unsigned lba_spare_sel : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		unsigned reserved13_18 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		unsigned bchst_trans : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		unsigned tr_rdy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		unsigned page_size : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		unsigned page_num : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		unsigned low_power : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		unsigned async_tog_mix : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		unsigned bypass_fifo_mode : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		unsigned reserved31_31 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	} V9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) union BCH_CTL_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	u32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		unsigned rst : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		unsigned reserved : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		unsigned addr_not_care : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		unsigned power_down : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		unsigned bch_mode : 1;	   /* 0-16bit/1KB, 1-24bit/1KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		unsigned region : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		unsigned addr : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		unsigned bchpage : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		unsigned reserved17 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		unsigned bch_mode1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		unsigned thres : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		unsigned reserved27_31 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	} V6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		unsigned bchrst : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		unsigned wcnt_clear : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		unsigned reserved2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		unsigned bchepd : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		unsigned reserved4_15 : 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		unsigned bchpage : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		unsigned bchthre : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		unsigned bchmode : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		unsigned reserved28_31 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	} V9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) union BCH_ST_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		unsigned errf0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		unsigned done0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		unsigned fail0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		unsigned err_bits0 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		unsigned err_bits_low0 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		unsigned errf1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		unsigned done1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		unsigned fail1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		unsigned err_bits1 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		unsigned err_bits_low1 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		unsigned rdy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		/* unsigned cnt : 1; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		unsigned err_bits0_5 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		unsigned err_bits_low0_5 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		unsigned err_bits1_5 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		unsigned err_bits_low1_5 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		unsigned reserved31_31 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	} V6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		unsigned errf0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		unsigned done0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		unsigned fail0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		unsigned err_bits0 : 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		unsigned all_f_flag0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		unsigned reserved11_15 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		unsigned errf1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		unsigned done1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		unsigned fail1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		unsigned err_bits1 : 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		unsigned all_f_flag1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		unsigned reserved27_30 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		unsigned bch_ready_flag: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	} V9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) union MTRANS_CFG_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	u32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		unsigned ahb_wr_st : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		unsigned ahb_wr : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		unsigned bus_mode : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		unsigned hsize : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		unsigned burst : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		unsigned incr_num : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		unsigned fl_pwd : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		unsigned ahb_rst : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		unsigned reserved16_31 : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	} V6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		unsigned ahb_wr_st : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		unsigned ahb_wr : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		unsigned bus_mode : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		unsigned hsize : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		unsigned burst : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		unsigned incr_num : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		unsigned fl_pwd : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		unsigned ahb_rst : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		unsigned redundance_size : 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		unsigned reserved27_31 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	} V9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) union MTRANS_STAT_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	u32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		unsigned bus_err : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		unsigned mtrans_cnt : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		unsigned reserved21_31 : 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	} V6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		unsigned bus_err : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		unsigned mtrans_cnt : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		unsigned reserved22_31 : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	} V9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* NANDC Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define NANDC_FMCTL		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define NANDC_FMWAIT		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define NANDC_FLCTL		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define NANDC_BCHCTL		0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define NANDC_MTRANS_CFG	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define NANDC_MTRANS_SADDR0	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define NANDC_MTRANS_SADDR1	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define NANDC_MTRANS_STAT	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define NANDC_DLL_CTL_REG0	0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define NANDC_DLL_CTL_REG1	0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define NANDC_DLL_OBS_REG0	0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define NANDC_RANDMZ_CFG	0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define NANDC_EBI_EN		0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define NANDC_FMWAIT_SYN	0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define NANDC_MTRANS_STAT2	0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define NANDC_NANDC_VER		0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define NANDC_LLP_CTL		0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define NANDC_LLP_STAT		0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define NANDC_INTEN		0x16c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define NANDC_INTCLR		0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define NANDC_INTST		0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define NANDC_SPARE0		0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define NANDC_SPARE1		0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define NANDC_BCHST(i)		({		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	u32 x = (i);				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	4 * x + x < 8 ? 0x20 : 0x520; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define NANDC_CHIP_DATA(id)	(0x800 + (id) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define NANDC_CHIP_ADDR(id)	(0x800 + (id) * 0x100 + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define NANDC_CHIP_CMD(id)	(0x800 + (id) * 0x100 + 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define NANDC_V9_FMCTL		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define NANDC_V9_FMWAIT		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define NANDC_V9_FLCTL		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define NANDC_V9_BCHCTL		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define NANDC_V9_MTRANS_CFG	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define NANDC_V9_MTRANS_SADDR0	0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define NANDC_V9_MTRANS_SADDR1	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define NANDC_V9_MTRANS_STAT	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define NANDC_V9_MTRANS_STAT2	0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define NANDC_V9_NANDC_VER	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define NANDC_V9_INTEN		0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define NANDC_V9_INTCLR		0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define NANDC_V9_INTST		0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define NANDC_V9_SPARE0		0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define NANDC_V9_SPARE1		0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define NANDC_V9_RANDMZ_CFG	0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define NANDC_V9_BCHST(i)	(0x150 + (i) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define NANDC_V9_CHIP_DATA(id)	(0x800 + (id) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define NANDC_V9_CHIP_ADDR(id)	(0x800 + (id) * 0x100 + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define NANDC_V9_CHIP_CMD(id)	(0x800 + (id) * 0x100 + 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct MASTER_INFO_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	u32  *page_buf;		/* [DATA_LEN]; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	u32  *spare_buf;	/* [DATA_LEN / (1024/128)]; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	u32  *page_vir;	/* page_buf_vir_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	u32  *spare_vir;	/* spare_buf_vir_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	u32  page_phy;		/* page_buf_phy_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	u32  spare_phy;	/* spare_buf_phy_addr*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	u32  mapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	u32  cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct CHIP_MAP_INFO_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	u32  *nandc_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	u32  chip_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned long rknandc_dma_map_single(unsigned long ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 				     int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 				     int dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) void rknandc_dma_unmap_single(unsigned long ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 			      int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			      int dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void nandc_init(void __iomem *nandc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) void nandc_flash_cs(u8 chip_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) void nandc_flash_de_cs(u8 chip_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 nandc_wait_flash_ready(u8 chip_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 nandc_delayns(u32 count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 nandc_xfer_data(u8 chip_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		    u8 dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		    u8 sector_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		    u32 *p_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		    u32 *p_spare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) void nandc_randmz_sel(u8 chip_sel, u32 randmz_seed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) void nandc_bch_sel(u8 bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) void nandc_read_not_case_busy_en(u8 en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) void nandc_time_cfg(u32 ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) void nandc_clean_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 nandc_get_version(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #endif