Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include "flash.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "rkflash_api.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "rk_sftl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static int sftl_flash_init(void __iomem *reg_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	ret = nandc_flash_init(reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		ret = sftl_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static unsigned int sftl_flash_get_capacity(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	return sftl_get_density();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static int sftl_flash_read(u32 sec, u32 n_sec, void *p_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	return sftl_read(sec, n_sec, p_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int sftl_flash_write(u32 sec, u32 n_sec, void *p_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	return sftl_write(sec, n_sec, p_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int sftl_flash_vendor_read(u32 sec, u32 n_sec, void *p_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	return sftl_vendor_read(sec, n_sec, p_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int sftl_flash_vendor_write(u32 sec, u32 n_sec, void *p_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	return sftl_vendor_write(sec, n_sec, p_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int sftl_flash_gc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	return sftl_gc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int sftl_flash_discard(u32 sec, u32 n_sec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	return sftl_discard(sec, n_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void sftl_flash_deinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	u8 chip_sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	sftl_deinit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	nandc_flash_reset(chip_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int sftl_flash_resume(void __iomem *reg_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	return nandc_flash_init(reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) const struct flash_boot_ops nandc_nand_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	sftl_flash_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	sftl_flash_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	sftl_flash_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	sftl_flash_get_capacity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	sftl_flash_deinit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	sftl_flash_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	sftl_flash_vendor_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	sftl_flash_vendor_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	sftl_flash_gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	sftl_flash_discard,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)