Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifndef __FLASH_COM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define __FLASH_COM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include "typedef.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define NAND_ERROR			INVALID_UINT32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define NAND_OK				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define NAND_STS_OK                     0	/* bit 0 ecc error or ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define NAND_STS_REFRESH                256	/* need refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define NAND_STS_EMPTY                  512	/* page is not proged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define NAND_STS_ECC_ERR                NAND_ERROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define NAND_IDB_START    64 /* 32 KB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define NAND_IDB_SIZE    512 /* 256 KB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define NAND_IDB_END    (NAND_IDB_START + NAND_IDB_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DEFAULT_IDB_RESERVED_BLOCK	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FULL_SLC			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SLC				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NAND_FLASH_MLC_PAGE_TAG         0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MAX_FLASH_PAGE_SIZE		0x1000 /* 4KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PAGE_ADDR_BITS			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PAGE_ADDR_MASK			((1u << 11) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BLOCK_ADDR_BITS			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BLOCK_ADDR_MASK			((1u << 14) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DIE_ADDR_BITS			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DIE_ADDR_MASK			((1u << 3) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FLAG_ADDR_BITS			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FLAG_ADDR_MASK			((1u << 4) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PHY_BLK_DIE_ADDR_BITS		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct nand_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	u32 page_addr;   /* 31:28 flag, 27:25: die, 24:11 block, 10:0 page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	u32 *p_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	u32 *p_spare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	u32 lpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct nand_phy_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	u16	nand_type;		/* SLC,MLC,TLC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	u16	die_num;		/* number of LUNs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	u16	plane_per_die;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	u16	blk_per_plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	u16	blk_per_die;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	u16	page_per_blk;		/* in MLC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	u16	page_per_slc_blk;	/* in SLC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	u16	sec_per_page;		/* physical page data size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	u16	sec_per_blk;		/* physical page data size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	u16	byte_per_sec;		/* size of logical sectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	u16	reserved_blk;		/* reserved for boot loader in die 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	u8	ecc_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct nand_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	s32 (*get_bad_blk_list)(u16 *table, u32 die);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	u32 (*erase_blk)(u8 cs, u32 page_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	u32 (*prog_page)(u8 cs, u32 page_addr, u32 *data, u32 *spare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	u32 (*read_page)(u8 cs, u32 page_addr, u32 *data, u32 *spare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	void (*bch_sel)(u8 bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	void (*set_sec_num)(u8 num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) s32 ftl_flash_prog_pages(void *req, u32 num_req, u32 flash_type, u32 check);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) s32 ftl_flash_read_pages(void *req, u32 num_req, u32 flash_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) s32 ftl_flash_erase_blocks(void *req, u32 num_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) s32 ftl_flash_test_blk(u16 phy_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) s32 ftl_flash_get_bad_blk_list(u16 *table, u32 die);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif