^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef __FLASH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define __FLASH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define BIT(nr) (1 << (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MAX_FLASH_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MAX_IDB_RESERVED_BLOCK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define NAND_CACHE_READ_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define NAND_CACHE_RANDOM_READ_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define NAND_CACHE_PROG_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define NAND_MULTI_READ_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define NAND_MULTI_PROG_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NAND_INTERLEAVE_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define NAND_READ_RETRY_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define NAND_RANDOMIZER_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NAND_INTER_MODE_OFFSET (0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NAND_INTER_MODE_MARK (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define NAND_INTER_SDR_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NAND_INTER_ONFI_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NAND_INTER_TOGGLE_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NAND_SDR_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define NAND_ONFI_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define NAND_TOGGLE_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NAND_UNIQUE_ID_EN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RESET_CMD 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define READ_ID_CMD 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define READ_STATUS_CMD 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PAGE_PROG_CMD 0x8010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BLOCK_ERASE_CMD 0x60d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define READ_CMD 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define READ_DP_OUT_CMD 0x05E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define READ_ECC_STATUS_CMD 0x7A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SAMSUNG 0x00 /* SAMSUNG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TOSHIBA 0x01 /* TOSHIBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HYNIX 0x02 /* HYNIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define INFINEON 0x03 /* INFINEON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MICRON 0x04 /* MICRON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RENESAS 0x05 /* RENESAS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ST 0x06 /* ST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define INTEL 0x07 /* intel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define Sandisk 0x08 /* Sandisk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RR_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RR_HY_1 0x01 /* hynix H27UCG8T2M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RR_HY_2 0x02 /* hynix H27UBG08U0B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RR_HY_3 0x03 /* hynix H27UCG08U0B H27UBG08U0C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RR_HY_4 0x04 /* hynix H27UCG8T2A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RR_HY_5 0x05 /* hynix H27UCG8T2E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RR_HY_6 0x06 /* hynix H27QCG8T2F5R-BCG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RR_MT_1 0x11 /* micron */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RR_MT_2 0x12 /* micron L94C L95B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RR_TH_1 0x21 /* toshiba */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RR_TH_2 0x22 /* toshiba */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RR_TH_3 0x23 /* toshiba */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RR_SS_1 0x31 /* samsung */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RR_SD_1 0x41 /* Sandisk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RR_SD_2 0x42 /* Sandisk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RR_SD_3 0x43 /* Sandisk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RR_SD_4 0x44 /* Sandisk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* 0 1 2 3 4 5 6 7 8 9 slc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LSB_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* 0 1 2 3 6 7 A B E F hynix, micron 74A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LSB_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* 0 1 3 5 7 9 B D toshiba samsung sandisk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LSB_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* 0 1 2 3 4 5 8 9 C D 10 11 micron 84A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LSB_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* 0 1 2 3 4 5 7 8 A B E F micron L95B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LSB_4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* 0 1 2 3 4 5 8 9 14 15 20 21 26 27 micron B74A TLC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LSB_6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* 0 3 6 9 C F 12 15 18 15 1B 1E 21 24 K9ABGD8U0C TLC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LSB_7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* BadBlockFlagMode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* first spare @ first page of each blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BBF_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* first spare @ last page of each blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BBF_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* first spare @ first and last page of each blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define BBF_11 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* sandisk 15nm flash prog first page without data and check status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BBF_3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MPM_0 0 /* block 0 ~ 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MPM_1 1 /* block 0 ~ 2048... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct NAND_PARA_INFO_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u8 id_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 nand_id[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 die_per_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 sec_per_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u16 page_per_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 cell; /* 1 slc , 2 mlc , 3 tlc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 plane_per_die;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 blk_per_plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u16 operation_opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 lsb_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 read_retry_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 ecc_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u8 access_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 opt_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 die_gap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 bad_block_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 multi_plane_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 reversd2[6]; /* 32 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) extern struct nand_phy_info g_nand_phy_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) extern struct nand_ops g_nand_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) extern void __iomem *nandc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void nandc_flash_get_id(u8 cs, void *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void nandc_flash_reset(u8 chip_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 nandc_flash_init(void __iomem *nandc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 nandc_flash_deinit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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