Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #define pr_fmt(fmt) "nandc: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "flash.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "flash_com.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "nandc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "rkflash_debug.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define FLASH_STRESS_TEST_EN		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) static u8 id_byte[MAX_FLASH_NUM][8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static u8 die_cs_index[MAX_FLASH_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static u8 g_nand_max_die;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static u16 g_totle_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static u8 g_nand_flash_ecc_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static u8 g_nand_idb_res_blk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static u8 g_nand_ecc_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static struct NAND_PARA_INFO_T nand_para = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	{0x98, 0xF1, 0, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	TOSHIBA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	LSB_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	RR_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	BBF_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	MPM_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	{0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };	/* TC58NVG0S3HTA00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static void flash_read_id_raw(u8 cs, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u8 *ptr = (u8 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	nandc_flash_reset(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	nandc_flash_cs(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	nandc_writel(0x00, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	nandc_delayns(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	ptr[3] = nandc_readl(NANDC_CHIP_DATA(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	ptr[4] = nandc_readl(NANDC_CHIP_DATA(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	ptr[5] = nandc_readl(NANDC_CHIP_DATA(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	ptr[6] = nandc_readl(NANDC_CHIP_DATA(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	ptr[7] = nandc_readl(NANDC_CHIP_DATA(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	nandc_flash_de_cs(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (ptr[0] != 0xFF && ptr[0] && ptr[1] != 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		rkflash_print_error("No.%d FLASH ID:%x %x %x %x %x %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 				    cs + 1, ptr[0], ptr[1], ptr[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 				    ptr[3], ptr[4], ptr[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static void flash_bch_sel(u8 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	g_nand_flash_ecc_bits = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	nandc_bch_sel(bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static void flash_set_sector(u8 num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	nand_para.sec_per_page = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static __maybe_unused void flash_timing_cfg(u32 ahb_khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	nandc_time_cfg(nand_para.access_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static void flash_read_cmd(u8 cs, u32 page_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	nandc_writel(READ_CMD >> 8, NANDC_CHIP_CMD(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	nandc_writel(0x00, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	nandc_writel(0x00, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	nandc_writel(READ_CMD & 0x00ff, NANDC_CHIP_CMD(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void flash_prog_first_cmd(u8 cs, u32 page_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	nandc_writel(PAGE_PROG_CMD >> 8, NANDC_CHIP_CMD(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	nandc_writel(0x00, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	nandc_writel(0x00, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void flash_erase_cmd(u8 cs, u32 page_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	nandc_writel(BLOCK_ERASE_CMD >> 8, NANDC_CHIP_CMD(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	nandc_writel(BLOCK_ERASE_CMD & 0x00ff, NANDC_CHIP_CMD(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void flash_prog_second_cmd(u8 cs, u32 page_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	usleep_range(100, 120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	nandc_writel(PAGE_PROG_CMD & 0x00ff, NANDC_CHIP_CMD(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static u32 flash_read_status(u8 cs, u32 page_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	nandc_writel(READ_STATUS_CMD, NANDC_CHIP_CMD(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	nandc_delayns(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return nandc_readl(NANDC_CHIP_DATA(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void flash_read_random_dataout_cmd(u8 cs, u32 col_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	nandc_writel(READ_DP_OUT_CMD >> 8, NANDC_CHIP_CMD(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	nandc_writel(col_addr & 0x00ff, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	nandc_writel(col_addr >> 8, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	nandc_writel(READ_DP_OUT_CMD & 0x00ff, NANDC_CHIP_CMD(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static u32 flash_read_ecc(u8 cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	u32 ecc0, ecc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	nandc_writel(READ_ECC_STATUS_CMD, NANDC_CHIP_CMD(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	nandc_delayns(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	ecc0 = nandc_readl(NANDC_CHIP_DATA(cs)) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ecc1 = nandc_readl(NANDC_CHIP_DATA(cs)) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (ecc1 > ecc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		ecc0 = ecc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ecc1 = nandc_readl(NANDC_CHIP_DATA(cs)) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (ecc1 > ecc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		ecc0 = ecc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ecc1 = nandc_readl(NANDC_CHIP_DATA(cs)) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (ecc1 > ecc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		ecc0 = ecc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	return ecc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static u32 flash_read_page_raw(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u32 error_ecc_bits, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	u32 sec_per_page = nand_para.sec_per_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u32 nand_ecc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	nandc_wait_flash_ready(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	nandc_flash_cs(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	flash_read_cmd(cs, page_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	nandc_wait_flash_ready(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	flash_read_random_dataout_cmd(cs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	nandc_wait_flash_ready(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	error_ecc_bits = nandc_xfer_data(cs, NANDC_READ, sec_per_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 					 p_data, p_spare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	nandc_flash_de_cs(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (error_ecc_bits != NAND_STS_ECC_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		if (error_ecc_bits >= (u32)nand_para.ecc_bits - 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			ret = NAND_STS_REFRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			ret = NAND_STS_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			if (g_nand_ecc_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				nand_ecc = flash_read_ecc(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				if (nand_ecc >= 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 					rkflash_print_error("%s nand ecc %x ecc %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 							    __func__, page_addr, nand_ecc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 					ret = NAND_STS_REFRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		ret = NAND_STS_ECC_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (nand_ecc > 4 || error_ecc_bits > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		rkflash_print_info("%s %x %x nandc ecc= %d, internal ecc= %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 				   __func__, cs, page_addr, error_ecc_bits, nand_ecc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static u32 flash_read_page(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	u32 ret, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	ret = flash_read_page_raw(cs, page_addr, p_data, p_spare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (ret == NAND_STS_ECC_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		for (; i < 50; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			ret = flash_read_page_raw(cs, page_addr, p_data, p_spare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			if (ret != NAND_STS_ECC_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 				ret = NAND_STS_REFRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		rkflash_print_error("%s %x err_ecc %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 				    __func__, page_addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	rkflash_print_dio("%s %x %x retry=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			  __func__, page_addr, p_data[0], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static u32 flash_prog_page(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	u32 sec_per_page = nand_para.sec_per_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	rkflash_print_dio("%s %x %x\n", __func__, page_addr, p_data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	nandc_wait_flash_ready(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	nandc_flash_cs(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	flash_prog_first_cmd(cs, page_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	nandc_xfer_data(cs, NANDC_WRITE, sec_per_page, p_data, p_spare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	flash_prog_second_cmd(cs, page_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	nandc_wait_flash_ready(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	status = flash_read_status(cs, page_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	nandc_flash_de_cs(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	status &= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		rkflash_print_info("%s addr=%x status=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 				   __func__, page_addr, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static u32 flash_erase_block(u8 cs, u32 page_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	rkflash_print_dio("%s %x\n", __func__, page_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	nandc_wait_flash_ready(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	nandc_flash_cs(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	flash_erase_cmd(cs, page_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	nandc_wait_flash_ready(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	status = flash_read_status(cs, page_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	nandc_flash_de_cs(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	status &= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		rkflash_print_info("%s pageadd=%x status=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				   __func__, page_addr, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void flash_read_spare(u8 cs, u32 page_addr, u8 *spare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	u32 col = nand_para.sec_per_page << 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	nandc_writel(READ_CMD >> 8, NANDC_CHIP_CMD(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	nandc_writel(col, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	nandc_writel(col >> 8, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	nandc_writel(READ_CMD & 0x00ff, NANDC_CHIP_CMD(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	nandc_wait_flash_ready(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	*spare = nandc_readl(NANDC_CHIP_DATA(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  * Read the 1st page's 1st spare byte of a phy_blk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  * If not FF, it's bad blk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static s32 flash_get_bad_blk_list(u16 *table, u32 die)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	u16 blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	u32 bad_cnt, page_addr0, page_addr1, page_addr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	u32 blk_per_die;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	u8 bad_flag0, bad_flag1, bad_flag2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	bad_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	blk_per_die = nand_para.plane_per_die * nand_para.blk_per_plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	for (blk = 0; blk < blk_per_die; blk++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		bad_flag0 = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		bad_flag1 = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		bad_flag2 = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		page_addr0 = (blk + blk_per_die * die) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			nand_para.page_per_blk + 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		page_addr1 = page_addr0 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		page_addr2 = page_addr0 + nand_para.page_per_blk - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		flash_read_spare(die, page_addr0, &bad_flag0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		flash_read_spare(die, page_addr1, &bad_flag1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		flash_read_spare(die, page_addr2, &bad_flag2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		if (bad_flag0 != 0xFF ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		    bad_flag1 != 0xFF ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		    bad_flag2 != 0xFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			table[bad_cnt++] = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			rkflash_print_error("die[%d], bad_blk[%d]\n", die, blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	return bad_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void flash_die_info_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	u32 cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	g_nand_max_die = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	for (cs = 0; cs < MAX_FLASH_NUM; cs++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		if (nand_para.nand_id[1] == id_byte[cs][1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 			die_cs_index[g_nand_max_die] = cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			g_nand_max_die++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	g_totle_block = g_nand_max_die *  nand_para.plane_per_die *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			nand_para.blk_per_plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void flash_show_info(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	rkflash_print_info("No.0 FLASH ID: %x %x %x %x %x %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			   nand_para.nand_id[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			   nand_para.nand_id[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			   nand_para.nand_id[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			   nand_para.nand_id[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			   nand_para.nand_id[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			   nand_para.nand_id[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	rkflash_print_info("die_per_chip: %x\n", nand_para.die_per_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	rkflash_print_info("sec_per_page: %x\n", nand_para.sec_per_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	rkflash_print_info("page_per_blk: %x\n", nand_para.page_per_blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	rkflash_print_info("cell: %x\n", nand_para.cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	rkflash_print_info("plane_per_die: %x\n", nand_para.plane_per_die);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	rkflash_print_info("blk_per_plane: %x\n", nand_para.blk_per_plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	rkflash_print_info("TotleBlock: %x\n", g_totle_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	rkflash_print_info("die gap: %x\n", nand_para.die_gap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	rkflash_print_info("lsb_mode: %x\n", nand_para.lsb_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	rkflash_print_info("read_retry_mode: %x\n", nand_para.read_retry_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	rkflash_print_info("ecc_bits: %x\n", nand_para.ecc_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	rkflash_print_info("Use ecc_bits: %x\n", g_nand_flash_ecc_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	rkflash_print_info("access_freq: %x\n", nand_para.access_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	rkflash_print_info("opt_mode: %x\n", nand_para.opt_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	rkflash_print_info("Cache read enable: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			   nand_para.operation_opt & NAND_CACHE_READ_EN ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	rkflash_print_info("Cache random read enable: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			   nand_para.operation_opt &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			   NAND_CACHE_RANDOM_READ_EN ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	rkflash_print_info("Cache prog enable: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 			   nand_para.operation_opt & NAND_CACHE_PROG_EN ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	rkflash_print_info("multi read enable: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			   nand_para.operation_opt & NAND_MULTI_READ_EN ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	rkflash_print_info("multi prog enable: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			   nand_para.operation_opt & NAND_MULTI_PROG_EN ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	rkflash_print_info("interleave enable: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			   nand_para.operation_opt & NAND_INTERLEAVE_EN ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	rkflash_print_info("read retry enable: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 			   nand_para.operation_opt & NAND_READ_RETRY_EN ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	rkflash_print_info("randomizer enable: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			   nand_para.operation_opt & NAND_RANDOMIZER_EN ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	rkflash_print_info("SDR enable: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 			   nand_para.operation_opt & NAND_SDR_EN ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	rkflash_print_info("ONFI enable: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 			   nand_para.operation_opt & NAND_ONFI_EN ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	rkflash_print_info("TOGGLE enable: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			   nand_para.operation_opt & NAND_TOGGLE_EN ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	rkflash_print_info("g_nand_idb_res_blk_num: %x\n", g_nand_idb_res_blk_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static void flash_ftl_ops_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	u8 nandc_ver = nandc_get_version();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	/* para init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	g_nand_phy_info.nand_type	= nand_para.cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	g_nand_phy_info.die_num		= nand_para.die_per_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	g_nand_phy_info.plane_per_die	= nand_para.plane_per_die;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	g_nand_phy_info.blk_per_plane	= nand_para.blk_per_plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	g_nand_phy_info.page_per_blk	= nand_para.page_per_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	g_nand_phy_info.page_per_slc_blk	= nand_para.page_per_blk /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 						  nand_para.cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	g_nand_phy_info.byte_per_sec	= 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	g_nand_phy_info.sec_per_page	= nand_para.sec_per_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	g_nand_phy_info.sec_per_blk	= nand_para.sec_per_page *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 					  nand_para.page_per_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	g_nand_phy_info.reserved_blk	= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	g_nand_phy_info.blk_per_die	= nand_para.plane_per_die *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 					  nand_para.blk_per_plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	g_nand_phy_info.ecc_bits	= nand_para.ecc_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	/* driver register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	g_nand_ops.get_bad_blk_list	= flash_get_bad_blk_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	g_nand_ops.erase_blk		= flash_erase_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	g_nand_ops.prog_page		= flash_prog_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	g_nand_ops.read_page		= flash_read_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	if (nandc_ver == 9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		g_nand_ops.bch_sel = flash_bch_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		g_nand_ops.set_sec_num = flash_set_sector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) void nandc_flash_reset(u8 cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	nandc_flash_cs(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	nandc_writel(RESET_CMD, NANDC_CHIP_CMD(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	nandc_wait_flash_ready(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	nandc_flash_de_cs(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u32 nandc_flash_init(void __iomem *nandc_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	u32 cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	rkflash_print_error("...%s enter...\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	g_nand_idb_res_blk_num = MAX_IDB_RESERVED_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	g_nand_ecc_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	nandc_init(nandc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	for (cs = 0; cs < MAX_FLASH_NUM; cs++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		flash_read_id_raw(cs, id_byte[cs]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		if (cs == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 			if (id_byte[0][0] == 0xFF ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 			    id_byte[0][0] == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 			    id_byte[0][1] == 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 				return FTL_NO_FLASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 			if (id_byte[0][1] != 0xF1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 			    id_byte[0][1] != 0xDA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 			    id_byte[0][1] != 0xD1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 			    id_byte[0][1] != 0x95 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 			    id_byte[0][1] != 0xDC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 			    id_byte[0][1] != 0xD3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 			    id_byte[0][1] != 0x48 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 			    id_byte[0][1] != 0xA1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 			    id_byte[0][1] != 0xAA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 			    id_byte[0][1] != 0xAC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 			    id_byte[0][1] != 0x6A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 				pr_err("The device not support yet!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 				return FTL_UNSUPPORTED_FLASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	if (id_byte[0][0] == 0x98 && (id_byte[0][4] & 0x80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		g_nand_ecc_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	nand_para.nand_id[1] = id_byte[0][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	if (id_byte[0][1] == 0xDA || id_byte[0][1] == 0xAA || id_byte[0][1] == 0x6A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		nand_para.plane_per_die = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		nand_para.nand_id[1] = id_byte[0][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	} else if (id_byte[0][1] == 0xDC || id_byte[0][1] == 0xAC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		nand_para.nand_id[1] = id_byte[0][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		if ((id_byte[0][0] == 0x2C && id_byte[0][3] == 0xA6) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		    (id_byte[0][0] == 0xC2 && id_byte[0][3] == 0xA2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 			nand_para.plane_per_die = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 			nand_para.sec_per_page = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		} else if ((id_byte[0][0] == 0x98 && id_byte[0][3] == 0x26) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 			   (id_byte[0][0] == 0xC8 && ((id_byte[0][3] & 0x3) == 1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 			nand_para.blk_per_plane = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 			nand_para.sec_per_page = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 			nand_para.plane_per_die = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 			nand_para.plane_per_die = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 			nand_para.blk_per_plane = 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	} else if (id_byte[0][1] == 0x48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		nand_para.sec_per_page = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		nand_para.page_per_blk = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		nand_para.plane_per_die = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		nand_para.blk_per_plane = 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	} else if (id_byte[0][1] == 0xD3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		nand_para.sec_per_page = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		nand_para.page_per_blk = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		nand_para.plane_per_die = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		nand_para.blk_per_plane = 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	flash_die_info_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	flash_bch_sel(nand_para.ecc_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	flash_show_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	flash_ftl_ops_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) void nandc_flash_get_id(u8 cs, void *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	memcpy(buf, id_byte[cs], 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 nandc_flash_deinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }