Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2016 NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <soc/tegra/bpmp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <soc/tegra/bpmp-abi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) static struct tegra_bpmp *to_tegra_bpmp(struct reset_controller_dev *rstc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	return container_of(rstc, struct tegra_bpmp, rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static int tegra_bpmp_reset_common(struct reset_controller_dev *rstc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 				   enum mrq_reset_commands command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 				   unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	struct tegra_bpmp *bpmp = to_tegra_bpmp(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	struct mrq_reset_request request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	struct tegra_bpmp_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	memset(&request, 0, sizeof(request));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	request.cmd = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	request.reset_id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	memset(&msg, 0, sizeof(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	msg.mrq = MRQ_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	msg.tx.data = &request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	msg.tx.size = sizeof(request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	return tegra_bpmp_transfer(bpmp, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int tegra_bpmp_reset_module(struct reset_controller_dev *rstc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 				   unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	return tegra_bpmp_reset_common(rstc, CMD_RESET_MODULE, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int tegra_bpmp_reset_assert(struct reset_controller_dev *rstc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 				   unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	return tegra_bpmp_reset_common(rstc, CMD_RESET_ASSERT, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int tegra_bpmp_reset_deassert(struct reset_controller_dev *rstc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 				     unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	return tegra_bpmp_reset_common(rstc, CMD_RESET_DEASSERT, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const struct reset_control_ops tegra_bpmp_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	.reset = tegra_bpmp_reset_module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	.assert = tegra_bpmp_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	.deassert = tegra_bpmp_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int tegra_bpmp_init_resets(struct tegra_bpmp *bpmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	bpmp->rstc.ops = &tegra_bpmp_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	bpmp->rstc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	bpmp->rstc.of_node = bpmp->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	bpmp->rstc.nr_resets = bpmp->soc->num_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	return devm_reset_controller_register(bpmp->dev, &bpmp->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }