Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2013 STMicroelectronics (R&D) Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Stephen Gallimore <stephen.gallimore@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __STI_RESET_SYSCFG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __STI_RESET_SYSCFG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * Reset channel description for a system configuration register based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * reset controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * @compatible: Compatible string of the syscon regmap containing this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  *              channel's control and ack (status) bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * @reset: Regmap field description of the channel's reset bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * @ack: Regmap field description of the channel's acknowledge bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct syscfg_reset_channel_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	const char *compatible;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	struct reg_field reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	struct reg_field ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	{ .compatible	= _c,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	  .reset	= REG_FIELD(_rr, _rb, _rb),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	  .ack		= REG_FIELD(_ar, _ab, _ab), }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	{ .compatible	= _c,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	  .reset	= REG_FIELD(_rr, _rb, _rb), }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  * Description of a system configuration register based reset controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  * @wait_for_ack: The controller will wait for reset assert and de-assert to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  *                be "ack'd" in a channel's ack field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  * @active_low: Are the resets in this controller active low, i.e. clearing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  *              the reset bit puts the hardware into reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  * @nr_channels: The number of reset channels in this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)  * @channels: An array of reset channel descriptions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct syscfg_reset_controller_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	bool wait_for_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	bool active_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	int nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	const struct syscfg_reset_channel_data *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  * syscfg_reset_probe(): platform device probe function used by syscfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)  *                       reset controller drivers. This registers a reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)  *                       controller configured by the OF match data for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)  *                       the compatible device which should be of type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)  *                       "struct syscfg_reset_controller_data".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)  * @pdev: platform device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int syscfg_reset_probe(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif /* __STI_RESET_SYSCFG_H */