Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2014 STMicroelectronics (R&D) Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <dt-bindings/reset/stih407-resets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "reset-syscfg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* STiH407 Peripheral powerdown definitions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) static const char stih407_core[] = "st,stih407-core-syscfg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) static const char stih407_lpm[] = "st,stih407-lpm-syscfg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define STIH407_PDN_0(_bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	_SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define STIH407_PDN_1(_bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	_SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define STIH407_PDN_ETH(_bit, _stat) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	_SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* Powerdown requests control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SYSCFG_5000	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SYSSTAT_5500	0x7d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* Powerdown requests control 1 (High Speed Links) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SYSCFG_5001	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SYSSTAT_5501	0x7d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* Ethernet powerdown/status/reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SYSCFG_4032	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SYSSTAT_4520	0x820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SYSCFG_4002	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static const struct syscfg_reset_channel_data stih407_powerdowns[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	[STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	[STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	[STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	[STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	[STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	[STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	[STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	[STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	[STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	[STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* Reset Generator control 0/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SYSCFG_5128	0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SYSCFG_5131	0x20c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SYSCFG_5132	0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define LPM_SYSCFG_1	0x4	/* Softreset IRB & SBC UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define STIH407_SRST_CORE(_reg, _bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	_SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define STIH407_SRST_SBC(_reg, _bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	_SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define STIH407_SRST_LPM(_reg, _bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	_SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static const struct syscfg_reset_channel_data stih407_softresets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	[STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	[STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	[STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	[STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	[STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	[STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	[STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	[STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	[STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	[STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	[STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	[STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	[STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	[STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	[STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	[STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	[STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	[STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	[STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	[STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	[STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	[STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	[STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	[STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	[STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	[STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	[STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	[STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	[STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	[STIH407_ST231_AUD_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	[STIH407_ST231_DMU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	[STIH407_ST231_GP0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	[STIH407_ST231_GP1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5128, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* PicoPHY reset/control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SYSCFG_5061	0x0f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct syscfg_reset_channel_data stih407_picophyresets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	[STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	[STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	[STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct syscfg_reset_controller_data stih407_powerdown_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.wait_for_ack = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.nr_channels = ARRAY_SIZE(stih407_powerdowns),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.channels = stih407_powerdowns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct syscfg_reset_controller_data stih407_softreset_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.wait_for_ack = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.active_low = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	.nr_channels = ARRAY_SIZE(stih407_softresets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.channels = stih407_softresets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct syscfg_reset_controller_data stih407_picophyreset_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.wait_for_ack = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.nr_channels = ARRAY_SIZE(stih407_picophyresets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.channels = stih407_picophyresets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const struct of_device_id stih407_reset_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		.compatible = "st,stih407-powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.data = &stih407_powerdown_controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.compatible = "st,stih407-softreset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		.data = &stih407_softreset_controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.compatible = "st,stih407-picophyreset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.data = &stih407_picophyreset_controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct platform_driver stih407_reset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.probe = syscfg_reset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		.name = "reset-stih407",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.of_match_table = stih407_reset_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int __init stih407_reset_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return platform_driver_register(&stih407_reset_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) arch_initcall(stih407_reset_init);