^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015, National Instruments Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Xilinx Zynq Reset controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Moritz Fischer <moritz.fischer@ettus.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct zynq_reset_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct regmap *slcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define to_zynq_reset_data(p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) container_of((p), struct zynq_reset_data, rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int zynq_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int bank = id / BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int offset = id % BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return regmap_update_bits(priv->slcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) priv->offset + (bank * 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) BIT(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int zynq_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int bank = id / BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int offset = id % BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return regmap_update_bits(priv->slcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) priv->offset + (bank * 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) BIT(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ~BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int zynq_reset_status(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int bank = id / BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int offset = id % BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ret = regmap_read(priv->slcr, priv->offset + (bank * 4), ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return !!(reg & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct reset_control_ops zynq_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .assert = zynq_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .deassert = zynq_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .status = zynq_reset_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int zynq_reset_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct zynq_reset_data *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "syscon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (IS_ERR(priv->slcr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dev_err(&pdev->dev, "unable to get zynq-slcr regmap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return PTR_ERR(priv->slcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dev_err(&pdev->dev, "missing IO resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) priv->offset = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) priv->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) priv->rcdev.nr_resets = resource_size(res) / 4 * BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) priv->rcdev.ops = &zynq_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) priv->rcdev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct of_device_id zynq_reset_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { .compatible = "xlnx,zynq-reset", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct platform_driver zynq_reset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .probe = zynq_reset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .of_match_table = zynq_reset_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) builtin_platform_driver(zynq_reset_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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