^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct uniphier_reset_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define UNIPHIER_RESET_ID_END (unsigned int)(-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define UNIPHIER_RESET_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { .id = UNIPHIER_RESET_ID_END }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UNIPHIER_RESET(_id, _reg, _bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .id = (_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .reg = (_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .bit = (_bit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UNIPHIER_RESETX(_id, _reg, _bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .id = (_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .reg = (_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .bit = (_bit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .flags = UNIPHIER_RESET_ACTIVE_LOW, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* System reset data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const struct uniphier_reset_data uniphier_ld4_sys_reset_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) UNIPHIER_RESET_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) UNIPHIER_RESETX(29, 0x2004, 18), /* SATA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) UNIPHIER_RESETX(30, 0x2000, 19), /* SATA-PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) UNIPHIER_RESET_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (PCIe, USB3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) UNIPHIER_RESETX(24, 0x2008, 2), /* PCIe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) UNIPHIER_RESET_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, RLE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) UNIPHIER_RESET(30, 0x2014, 8), /* SATA-PHY (active high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) UNIPHIER_RESET_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) UNIPHIER_RESETX(6, 0x200c, 6), /* Ether */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC, MIO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) UNIPHIER_RESETX(9, 0x200c, 9), /* HSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) UNIPHIER_RESETX(40, 0x2008, 0), /* AIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) UNIPHIER_RESETX(41, 0x2008, 1), /* EVEA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) UNIPHIER_RESETX(42, 0x2010, 2), /* EXIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) UNIPHIER_RESET_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) UNIPHIER_RESETX(6, 0x200c, 6), /* Ether */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) UNIPHIER_RESETX(9, 0x200c, 9), /* HSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) UNIPHIER_RESETX(14, 0x200c, 5), /* USB30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) UNIPHIER_RESETX(19, 0x200c, 15), /* USB30-PHY3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) UNIPHIER_RESETX(24, 0x200c, 4), /* PCIe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) UNIPHIER_RESETX(40, 0x2008, 0), /* AIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) UNIPHIER_RESETX(41, 0x2008, 1), /* EVEA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) UNIPHIER_RESETX(42, 0x2010, 2), /* EXIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) UNIPHIER_RESET_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) UNIPHIER_RESETX(6, 0x200c, 9), /* Ether0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) UNIPHIER_RESETX(7, 0x200c, 10), /* Ether1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) UNIPHIER_RESETX(17, 0x200c, 18), /* USB30-PHY1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) UNIPHIER_RESETX(24, 0x200c, 3), /* PCIe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) UNIPHIER_RESETX(28, 0x200c, 7), /* SATA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) UNIPHIER_RESETX(29, 0x200c, 8), /* SATA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) UNIPHIER_RESETX(30, 0x200c, 21), /* SATA-PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) UNIPHIER_RESET_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Media I/O reset data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define UNIPHIER_MIO_RESET_SD(id, ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define UNIPHIER_MIO_RESET_USB2(id, ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define UNIPHIER_MIO_RESET_DMAC(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) UNIPHIER_RESETX((id), 0x110, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct uniphier_reset_data uniphier_ld4_mio_reset_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) UNIPHIER_MIO_RESET_SD(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) UNIPHIER_MIO_RESET_SD(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) UNIPHIER_MIO_RESET_SD(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) UNIPHIER_MIO_RESET_SD_BRIDGE(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) UNIPHIER_MIO_RESET_SD_BRIDGE(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) UNIPHIER_MIO_RESET_SD_BRIDGE(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) UNIPHIER_MIO_RESET_DMAC(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) UNIPHIER_MIO_RESET_USB2(8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) UNIPHIER_MIO_RESET_USB2(9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) UNIPHIER_MIO_RESET_USB2(10, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) UNIPHIER_MIO_RESET_USB2_BRIDGE(12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) UNIPHIER_MIO_RESET_USB2_BRIDGE(13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) UNIPHIER_MIO_RESET_USB2_BRIDGE(14, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) UNIPHIER_RESET_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) UNIPHIER_MIO_RESET_SD(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) UNIPHIER_MIO_RESET_SD(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) UNIPHIER_RESET_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Peripheral reset data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define UNIPHIER_PERI_RESET_UART(id, ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) UNIPHIER_RESETX((id), 0x114, 19 + (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define UNIPHIER_PERI_RESET_I2C(id, ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) UNIPHIER_RESETX((id), 0x114, 5 + (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define UNIPHIER_PERI_RESET_FI2C(id, ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) UNIPHIER_RESETX((id), 0x114, 24 + (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define UNIPHIER_PERI_RESET_SCSSI(id, ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) UNIPHIER_RESETX((id), 0x110, 17 + (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define UNIPHIER_PERI_RESET_MCSSI(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) UNIPHIER_RESETX((id), 0x114, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) UNIPHIER_PERI_RESET_UART(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) UNIPHIER_PERI_RESET_UART(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) UNIPHIER_PERI_RESET_UART(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) UNIPHIER_PERI_RESET_UART(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) UNIPHIER_PERI_RESET_I2C(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) UNIPHIER_PERI_RESET_I2C(5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) UNIPHIER_PERI_RESET_I2C(6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) UNIPHIER_PERI_RESET_I2C(7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) UNIPHIER_PERI_RESET_I2C(8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) UNIPHIER_PERI_RESET_SCSSI(11, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) UNIPHIER_RESET_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) UNIPHIER_PERI_RESET_UART(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) UNIPHIER_PERI_RESET_UART(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) UNIPHIER_PERI_RESET_UART(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) UNIPHIER_PERI_RESET_UART(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) UNIPHIER_PERI_RESET_FI2C(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) UNIPHIER_PERI_RESET_FI2C(5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) UNIPHIER_PERI_RESET_FI2C(6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) UNIPHIER_PERI_RESET_FI2C(7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) UNIPHIER_PERI_RESET_FI2C(8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) UNIPHIER_PERI_RESET_FI2C(9, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) UNIPHIER_PERI_RESET_FI2C(10, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) UNIPHIER_PERI_RESET_SCSSI(11, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) UNIPHIER_PERI_RESET_SCSSI(12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) UNIPHIER_PERI_RESET_SCSSI(13, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) UNIPHIER_PERI_RESET_SCSSI(14, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) UNIPHIER_PERI_RESET_MCSSI(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) UNIPHIER_RESET_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Analog signal amplifiers reset data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const struct uniphier_reset_data uniphier_ld11_adamv_reset_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) UNIPHIER_RESETX(0, 0x10, 6), /* EVEA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) UNIPHIER_RESET_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* core implementaton */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct uniphier_reset_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) const struct uniphier_reset_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define to_uniphier_reset_priv(_rcdev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) container_of(_rcdev, struct uniphier_reset_priv, rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int uniphier_reset_update(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned long id, int assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) const struct uniphier_reset_data *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (p->id != id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mask = BIT(p->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) val = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) val = ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) val = ~val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return regmap_write_bits(priv->regmap, p->reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dev_err(priv->dev, "reset_id=%lu was not handled\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int uniphier_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return uniphier_reset_update(rcdev, id, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int uniphier_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return uniphier_reset_update(rcdev, id, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int uniphier_reset_status(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) const struct uniphier_reset_data *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int ret, asserted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (p->id != id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = regmap_read(priv->regmap, p->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) asserted = !!(val & BIT(p->bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) asserted = !asserted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return asserted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_err(priv->dev, "reset_id=%lu was not found\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const struct reset_control_ops uniphier_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .assert = uniphier_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .deassert = uniphier_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .status = uniphier_reset_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int uniphier_reset_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct uniphier_reset_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) const struct uniphier_reset_data *p, *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct device_node *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned int nr_resets = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (WARN_ON(!data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) parent = of_get_parent(dev->of_node); /* parent should be syscon node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) regmap = syscon_node_to_regmap(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) of_node_put(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev_err(dev, "failed to get regmap (error %ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PTR_ERR(regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) for (p = data; p->id != UNIPHIER_RESET_ID_END; p++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) nr_resets = max(nr_resets, p->id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) priv->rcdev.ops = &uniphier_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) priv->rcdev.owner = dev->driver->owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) priv->rcdev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) priv->rcdev.nr_resets = nr_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) priv->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) priv->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const struct of_device_id uniphier_reset_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* System reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .compatible = "socionext,uniphier-ld4-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .data = uniphier_ld4_sys_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .compatible = "socionext,uniphier-pro4-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .data = uniphier_pro4_sys_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .compatible = "socionext,uniphier-sld8-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .data = uniphier_ld4_sys_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .compatible = "socionext,uniphier-pro5-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .data = uniphier_pro5_sys_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .compatible = "socionext,uniphier-pxs2-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .data = uniphier_pxs2_sys_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .compatible = "socionext,uniphier-ld11-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .data = uniphier_ld11_sys_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .compatible = "socionext,uniphier-ld20-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .data = uniphier_ld20_sys_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .compatible = "socionext,uniphier-pxs3-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .data = uniphier_pxs3_sys_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Media I/O reset, SD reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .compatible = "socionext,uniphier-ld4-mio-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .data = uniphier_ld4_mio_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .compatible = "socionext,uniphier-pro4-mio-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .data = uniphier_ld4_mio_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .compatible = "socionext,uniphier-sld8-mio-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .data = uniphier_ld4_mio_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .compatible = "socionext,uniphier-pro5-sd-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .data = uniphier_pro5_sd_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .compatible = "socionext,uniphier-pxs2-sd-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .data = uniphier_pro5_sd_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .compatible = "socionext,uniphier-ld11-mio-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .data = uniphier_ld4_mio_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .compatible = "socionext,uniphier-ld11-sd-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .data = uniphier_pro5_sd_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .compatible = "socionext,uniphier-ld20-sd-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .data = uniphier_pro5_sd_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .compatible = "socionext,uniphier-pxs3-sd-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .data = uniphier_pro5_sd_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Peripheral reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .compatible = "socionext,uniphier-ld4-peri-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .data = uniphier_ld4_peri_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .compatible = "socionext,uniphier-pro4-peri-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .data = uniphier_pro4_peri_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .compatible = "socionext,uniphier-sld8-peri-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .data = uniphier_ld4_peri_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .compatible = "socionext,uniphier-pro5-peri-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .data = uniphier_pro4_peri_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .compatible = "socionext,uniphier-pxs2-peri-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .data = uniphier_pro4_peri_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .compatible = "socionext,uniphier-ld11-peri-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .data = uniphier_pro4_peri_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .compatible = "socionext,uniphier-ld20-peri-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .data = uniphier_pro4_peri_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .compatible = "socionext,uniphier-pxs3-peri-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .data = uniphier_pro4_peri_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Analog signal amplifiers reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .compatible = "socionext,uniphier-ld11-adamv-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .data = uniphier_ld11_adamv_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .compatible = "socionext,uniphier-ld20-adamv-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .data = uniphier_ld11_adamv_reset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MODULE_DEVICE_TABLE(of, uniphier_reset_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static struct platform_driver uniphier_reset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .probe = uniphier_reset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .name = "uniphier-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .of_match_table = uniphier_reset_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) module_platform_driver(uniphier_reset_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MODULE_DESCRIPTION("UniPhier Reset Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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