^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copied from reset-sunxi.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/reset/reset-simple.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset/socfpga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SOCFPGA_NR_BANKS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static int a10_reset_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct reset_simple_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 reg_offset = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) data = kzalloc(sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ret = of_address_to_resource(np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) size = resource_size(&res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (!request_mem_region(res.start, size, np->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) data->membase = ioremap(res.start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (!data->membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (of_property_read_u32(np, "altr,modrst-offset", ®_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) pr_warn("missing altr,modrst-offset property, assuming 0x10\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) data->membase += reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) spin_lock_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) data->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) data->rcdev.nr_resets = SOCFPGA_NR_BANKS * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) data->rcdev.ops = &reset_simple_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) data->rcdev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) data->status_active_low = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return reset_controller_register(&data->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) err_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * These are the reset controller we need to initialize early on in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * our system, before we can even think of using a regular device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * driver for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * The controllers that we can register through the regular device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * model are handled by the simple reset driver directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const struct of_device_id socfpga_early_reset_dt_ids[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { .compatible = "altr,rst-mgr", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void __init socfpga_reset_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) for_each_matching_node(np, socfpga_early_reset_dt_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) a10_reset_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * The early driver is problematic, because it doesn't register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * itself as a driver. This causes certain device links to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * consumer devices from probing. The hacky solution is to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * an empty driver, whose only job is to attach itself to the reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * manager and call probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const struct of_device_id socfpga_reset_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { .compatible = "altr,rst-mgr", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int reset_simple_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct platform_driver reset_socfpga_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .probe = reset_simple_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .name = "socfpga-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .of_match_table = socfpga_reset_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) builtin_platform_driver(reset_socfpga_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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