^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/reset/qcom,sdm845-pdc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RPMH_PDC_SYNC_RESET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct qcom_pdc_reset_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct qcom_pdc_reset_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const struct regmap_config sdm845_pdc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .name = "pdc-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .max_register = 0x20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) [PDC_APPS_SYNC_RESET] = {0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) [PDC_SP_SYNC_RESET] = {1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) [PDC_AUDIO_SYNC_RESET] = {2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [PDC_SENSORS_SYNC_RESET] = {3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [PDC_AOP_SYNC_RESET] = {4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [PDC_DEBUG_SYNC_RESET] = {5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) [PDC_GPU_SYNC_RESET] = {6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [PDC_DISPLAY_SYNC_RESET] = {7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) [PDC_COMPUTE_SYNC_RESET] = {8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) [PDC_MODEM_SYNC_RESET] = {9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct reset_controller_dev *rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return container_of(rcdev, struct qcom_pdc_reset_data, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) BIT(sdm845_pdc_resets[idx].bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) BIT(sdm845_pdc_resets[idx].bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) BIT(sdm845_pdc_resets[idx].bit), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct reset_control_ops qcom_pdc_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .assert = qcom_pdc_control_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .deassert = qcom_pdc_control_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int qcom_pdc_reset_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct qcom_pdc_reset_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) data->regmap = devm_regmap_init_mmio(dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) &sdm845_pdc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (IS_ERR(data->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_err(dev, "Unable to initialize regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return PTR_ERR(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) data->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) data->rcdev.ops = &qcom_pdc_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) data->rcdev.nr_resets = ARRAY_SIZE(sdm845_pdc_resets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) data->rcdev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return devm_reset_controller_register(dev, &data->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const struct of_device_id qcom_pdc_reset_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { .compatible = "qcom,sdm845-pdc-global" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MODULE_DEVICE_TABLE(of, qcom_pdc_reset_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct platform_driver qcom_pdc_reset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .probe = qcom_pdc_reset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .name = "qcom_pdc_reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .of_match_table = qcom_pdc_reset_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) module_platform_driver(qcom_pdc_reset_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MODULE_DESCRIPTION("Qualcomm PDC Reset Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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