^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/reset/qcom,sdm845-aoss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct qcom_aoss_reset_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct qcom_aoss_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) const struct qcom_aoss_reset_map *resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) size_t num_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct qcom_aoss_reset_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) const struct qcom_aoss_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const struct qcom_aoss_reset_map sdm845_aoss_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) [AOSS_CC_MSS_RESTART] = {0x10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) [AOSS_CC_CAMSS_RESTART] = {0x11000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) [AOSS_CC_VENUS_RESTART] = {0x12000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) [AOSS_CC_GPU_RESTART] = {0x13000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) [AOSS_CC_DISPSS_RESTART] = {0x14000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) [AOSS_CC_WCSS_RESTART] = {0x20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) [AOSS_CC_LPASS_RESTART] = {0x30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct qcom_aoss_desc sdm845_aoss_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .resets = sdm845_aoss_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .num_resets = ARRAY_SIZE(sdm845_aoss_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static inline struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct reset_controller_dev *rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) writel(1, data->base + map->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Wait 6 32kHz sleep cycles for reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) usleep_range(200, 300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel(0, data->base + map->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Wait 6 32kHz sleep cycles for reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) usleep_range(200, 300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) qcom_aoss_control_assert(rcdev, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return qcom_aoss_control_deassert(rcdev, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const struct reset_control_ops qcom_aoss_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .reset = qcom_aoss_control_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .assert = qcom_aoss_control_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .deassert = qcom_aoss_control_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int qcom_aoss_reset_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct qcom_aoss_reset_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const struct qcom_aoss_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) desc = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) data->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) data->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (IS_ERR(data->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return PTR_ERR(data->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) data->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) data->rcdev.ops = &qcom_aoss_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) data->rcdev.nr_resets = desc->num_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) data->rcdev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return devm_reset_controller_register(dev, &data->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct of_device_id qcom_aoss_reset_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { .compatible = "qcom,sdm845-aoss-cc", .data = &sdm845_aoss_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MODULE_DEVICE_TABLE(of, qcom_aoss_reset_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct platform_driver qcom_aoss_reset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .probe = qcom_aoss_reset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .name = "qcom_aoss_reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .of_match_table = qcom_aoss_reset_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) module_platform_driver(qcom_aoss_reset_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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