^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Pistachio SoC Reset Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Imagination Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Damien Horsley <Damien.Horsley@imgtec.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/reset/pistachio-resets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PISTACHIO_SOFT_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct pistachio_reset_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct regmap *periph_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static inline int pistachio_reset_shift(unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) case PISTACHIO_RESET_I2C0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) case PISTACHIO_RESET_I2C1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) case PISTACHIO_RESET_I2C2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) case PISTACHIO_RESET_I2C3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) case PISTACHIO_RESET_I2S_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) case PISTACHIO_RESET_PRL_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) case PISTACHIO_RESET_SPDIF_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) case PISTACHIO_RESET_SPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) case PISTACHIO_RESET_PWM_PDM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) case PISTACHIO_RESET_UART0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) case PISTACHIO_RESET_UART1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) case PISTACHIO_RESET_QSPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) case PISTACHIO_RESET_MDC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) case PISTACHIO_RESET_SDHOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) case PISTACHIO_RESET_ETHERNET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) case PISTACHIO_RESET_IR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case PISTACHIO_RESET_HASH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) case PISTACHIO_RESET_TIMER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) case PISTACHIO_RESET_I2S_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case PISTACHIO_RESET_SPDIF_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) case PISTACHIO_RESET_EVT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return id + 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) case PISTACHIO_RESET_USB_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) case PISTACHIO_RESET_USB_PR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) case PISTACHIO_RESET_USB_PHY_PR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) case PISTACHIO_RESET_USB_PHY_PON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return id + 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int pistachio_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct pistachio_reset_data *rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) rd = container_of(rcdev, struct pistachio_reset_data, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) shift = pistachio_reset_shift(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (shift < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) mask = BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int pistachio_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct pistachio_reset_data *rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) rd = container_of(rcdev, struct pistachio_reset_data, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) shift = pistachio_reset_shift(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (shift < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mask = BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct reset_control_ops pistachio_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .assert = pistachio_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .deassert = pistachio_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int pistachio_reset_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct pistachio_reset_data *rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) rd = devm_kzalloc(dev, sizeof(*rd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (!rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) rd->periph_regs = syscon_node_to_regmap(np->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (IS_ERR(rd->periph_regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return PTR_ERR(rd->periph_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) rd->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) rd->rcdev.nr_resets = PISTACHIO_RESET_MAX + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) rd->rcdev.ops = &pistachio_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) rd->rcdev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return devm_reset_controller_register(dev, &rd->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct of_device_id pistachio_reset_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { .compatible = "img,pistachio-reset", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct platform_driver pistachio_reset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .probe = pistachio_reset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .name = "pistachio-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .of_match_table = pistachio_reset_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) builtin_platform_driver(pistachio_reset_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags