^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2019 Nuvoton Technology corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* NPCM7xx GCR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define NPCM_MDLR_OFFSET 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define NPCM_MDLR_USBD0 BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NPCM_MDLR_USBD1 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define NPCM_MDLR_USBD2_4 BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define NPCM_MDLR_USBD5_9 BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NPCM_USB1PHYCTL_OFFSET 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NPCM_USB2PHYCTL_OFFSET 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define NPCM_USBXPHYCTL_RS BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* NPCM7xx Reset registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define NPCM_SWRSTR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NPCM_SWRST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define NPCM_IPSRST1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NPCM_IPSRST1_USBD1 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define NPCM_IPSRST1_USBD2 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define NPCM_IPSRST1_USBD3 BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NPCM_IPSRST1_USBD4 BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define NPCM_IPSRST1_USBD5 BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NPCM_IPSRST1_USBD6 BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define NPCM_IPSRST2 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NPCM_IPSRST2_USB_HOST BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NPCM_IPSRST3 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NPCM_IPSRST3_USBD0 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NPCM_IPSRST3_USBD7 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define NPCM_IPSRST3_USBD8 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define NPCM_IPSRST3_USBD9 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define NPCM_IPSRST3_USBPHY1 BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define NPCM_IPSRST3_USBPHY2 BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NPCM_RC_RESETS_PER_REG 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define NPCM_MASK_RESETS GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct npcm_rc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct notifier_block restart_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 sw_reset_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define to_rc_data(p) container_of(p, struct npcm_rc_data, rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int npcm_rc_restart(struct notifier_block *nb, unsigned long mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct npcm_rc_data *rc = container_of(nb, struct npcm_rc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) restart_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) mdelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pr_emerg("%s: unable to restart system\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int npcm_rc_setclear_reset(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned long id, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct npcm_rc_data *rc = to_rc_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int ctrl_offset = id >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) spin_lock_irqsave(&rc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) stat = readl(rc->base + ctrl_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writel(stat | rst_bit, rc->base + ctrl_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel(stat & ~rst_bit, rc->base + ctrl_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) spin_unlock_irqrestore(&rc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int npcm_rc_assert(struct reset_controller_dev *rcdev, unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return npcm_rc_setclear_reset(rcdev, id, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int npcm_rc_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return npcm_rc_setclear_reset(rcdev, id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int npcm_rc_status(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct npcm_rc_data *rc = to_rc_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int ctrl_offset = id >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return (readl(rc->base + ctrl_offset) & rst_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const struct of_phandle_args *reset_spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int offset, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) offset = reset_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (offset != NPCM_IPSRST1 && offset != NPCM_IPSRST2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) offset != NPCM_IPSRST3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev_err(rcdev->dev, "Error reset register (0x%x)\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bit = reset_spec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (bit >= NPCM_RC_RESETS_PER_REG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_err(rcdev->dev, "Error reset number (%d)\n", bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return (offset << 8) | bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct of_device_id npcm_rc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { .compatible = "nuvoton,npcm750-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .data = (void *)"nuvoton,npcm750-gcr" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * The following procedure should be observed in USB PHY, USB device and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * USB host initialization at BMC boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 mdlr, iprst1, iprst2, iprst3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct regmap *gcr_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 ipsrst1_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 ipsrst3_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) const char *gcr_dt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) gcr_dt = (const char *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) of_match_device(dev->driver->of_match_table, dev)->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) gcr_regmap = syscon_regmap_lookup_by_compatible(gcr_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (IS_ERR(gcr_regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_err(&pdev->dev, "Failed to find %s\n", gcr_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return PTR_ERR(gcr_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* checking which USB device is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) regmap_read(gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (!(mdlr & NPCM_MDLR_USBD0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ipsrst3_bits |= NPCM_IPSRST3_USBD0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (!(mdlr & NPCM_MDLR_USBD1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ipsrst1_bits |= NPCM_IPSRST1_USBD1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!(mdlr & NPCM_MDLR_USBD2_4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ipsrst1_bits |= (NPCM_IPSRST1_USBD2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) NPCM_IPSRST1_USBD3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) NPCM_IPSRST1_USBD4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (!(mdlr & NPCM_MDLR_USBD0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ipsrst1_bits |= (NPCM_IPSRST1_USBD5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) NPCM_IPSRST1_USBD6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ipsrst3_bits |= (NPCM_IPSRST3_USBD7 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) NPCM_IPSRST3_USBD8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) NPCM_IPSRST3_USBD9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* assert reset USB PHY and USB devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) iprst1 = readl(rc->base + NPCM_IPSRST1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) iprst2 = readl(rc->base + NPCM_IPSRST2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) iprst3 = readl(rc->base + NPCM_IPSRST3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) iprst1 |= ipsrst1_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) iprst2 |= ipsrst2_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) NPCM_IPSRST3_USBPHY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) writel(iprst1, rc->base + NPCM_IPSRST1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) writel(iprst2, rc->base + NPCM_IPSRST2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel(iprst3, rc->base + NPCM_IPSRST3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* clear USB PHY RS bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) NPCM_USBXPHYCTL_RS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) NPCM_USBXPHYCTL_RS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* deassert reset USB PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) writel(iprst3, rc->base + NPCM_IPSRST3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* set USB PHY RS bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* deassert reset USB devices*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) iprst1 &= ~ipsrst1_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) iprst2 &= ~ipsrst2_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) iprst3 &= ~ipsrst3_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) writel(iprst1, rc->base + NPCM_IPSRST1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel(iprst2, rc->base + NPCM_IPSRST2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) writel(iprst3, rc->base + NPCM_IPSRST3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct reset_control_ops npcm_rc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .assert = npcm_rc_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .deassert = npcm_rc_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .status = npcm_rc_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int npcm_rc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct npcm_rc_data *rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) rc->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (IS_ERR(rc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return PTR_ERR(rc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) spin_lock_init(&rc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) rc->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) rc->rcdev.ops = &npcm_rc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) rc->rcdev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) rc->rcdev.of_reset_n_cells = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) rc->rcdev.of_xlate = npcm_reset_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) platform_set_drvdata(pdev, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_err(&pdev->dev, "unable to register device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (npcm_usb_reset(pdev, rc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_warn(&pdev->dev, "NPCM USB reset failed, can cause issues with UDC and USB host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!of_property_read_u32(pdev->dev.of_node, "nuvoton,sw-reset-number",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) &rc->sw_reset_number)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (rc->sw_reset_number && rc->sw_reset_number < 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) rc->restart_nb.priority = 192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rc->restart_nb.notifier_call = npcm_rc_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ret = register_restart_handler(&rc->restart_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_warn(&pdev->dev, "failed to register restart handler\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct platform_driver npcm_rc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .probe = npcm_rc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .name = "npcm-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .of_match_table = npcm_rc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) builtin_platform_driver(npcm_rc_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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