^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Amlogic Meson Reset Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BITS_PER_REG 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct meson_reset_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int reg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int level_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct meson_reset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) const struct meson_reset_param *param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int meson_reset_reset(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct meson_reset *data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) container_of(rcdev, struct meson_reset, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int bank = id / BITS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int offset = id % BITS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void __iomem *reg_addr = data->reg_base + (bank << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) writel(BIT(offset), reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int meson_reset_level(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long id, bool assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct meson_reset *data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) container_of(rcdev, struct meson_reset, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int bank = id / BITS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int offset = id % BITS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void __iomem *reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) reg_addr = data->reg_base + data->param->level_offset + (bank << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) spin_lock_irqsave(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) reg = readl(reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) writel(reg & ~BIT(offset), reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) writel(reg | BIT(offset), reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) spin_unlock_irqrestore(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int meson_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return meson_reset_level(rcdev, id, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int meson_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return meson_reset_level(rcdev, id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct reset_control_ops meson_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .reset = meson_reset_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .assert = meson_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .deassert = meson_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct meson_reset_param meson8b_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .reg_count = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .level_offset = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const struct meson_reset_param meson_a1_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .reg_count = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .level_offset = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct of_device_id meson_reset_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { .compatible = "amlogic,meson8b-reset", .data = &meson8b_param},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { .compatible = "amlogic,meson-gxbb-reset", .data = &meson8b_param},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { .compatible = "amlogic,meson-axg-reset", .data = &meson8b_param},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { .compatible = "amlogic,meson-a1-reset", .data = &meson_a1_param},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MODULE_DEVICE_TABLE(of, meson_reset_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int meson_reset_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct meson_reset *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) data->reg_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (IS_ERR(data->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return PTR_ERR(data->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) data->param = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!data->param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) platform_set_drvdata(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) spin_lock_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) data->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) data->rcdev.nr_resets = data->param->reg_count * BITS_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) data->rcdev.ops = &meson_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) data->rcdev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return devm_reset_controller_register(&pdev->dev, &data->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct platform_driver meson_reset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .probe = meson_reset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .name = "meson_reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .of_match_table = meson_reset_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) module_platform_driver(meson_reset_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MODULE_DESCRIPTION("Amlogic Meson Reset Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MODULE_LICENSE("Dual BSD/GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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