Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Reset driver for NXP LPC18xx/43xx Reset Generation Unit (RGU).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* LPC18xx RGU registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define LPC18XX_RGU_CTRL0		0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define LPC18XX_RGU_CTRL1		0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define LPC18XX_RGU_ACTIVE_STATUS0	0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LPC18XX_RGU_ACTIVE_STATUS1	0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define LPC18XX_RGU_RESETS_PER_REG	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* Internal reset outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LPC18XX_RGU_CORE_RST	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define LPC43XX_RGU_M0SUB_RST	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define LPC43XX_RGU_M0APP_RST	56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) struct lpc18xx_rgu_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct notifier_block restart_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct clk *clk_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct clk *clk_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define to_rgu_data(p) container_of(p, struct lpc18xx_rgu_data, rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static int lpc18xx_rgu_restart(struct notifier_block *nb, unsigned long mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			       void *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct lpc18xx_rgu_data *rc = container_of(nb, struct lpc18xx_rgu_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 						   restart_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	writel(BIT(LPC18XX_RGU_CORE_RST), rc->base + LPC18XX_RGU_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	mdelay(2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	pr_emerg("%s: unable to restart system\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * The LPC18xx RGU has mostly self-deasserting resets except for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * two reset lines going to the internal Cortex-M0 cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * To prevent the M0 core resets from accidentally getting deasserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * status register must be check and bits in control register set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * preserve the state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static int lpc18xx_rgu_setclear_reset(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 				      unsigned long id, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u32 stat_offset = LPC18XX_RGU_ACTIVE_STATUS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u32 ctrl_offset = LPC18XX_RGU_CTRL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u32 stat, rst_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	stat_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	ctrl_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	rst_bit = 1 << (id % LPC18XX_RGU_RESETS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	spin_lock_irqsave(&rc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	stat = ~readl(rc->base + stat_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		writel(stat | rst_bit, rc->base + ctrl_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		writel(stat & ~rst_bit, rc->base + ctrl_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	spin_unlock_irqrestore(&rc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static int lpc18xx_rgu_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			      unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	return lpc18xx_rgu_setclear_reset(rcdev, id, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static int lpc18xx_rgu_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 				unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	return lpc18xx_rgu_setclear_reset(rcdev, id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Only M0 cores require explicit reset deassert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int lpc18xx_rgu_reset(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			     unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	lpc18xx_rgu_assert(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	udelay(rc->delay_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	case LPC43XX_RGU_M0SUB_RST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	case LPC43XX_RGU_M0APP_RST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		lpc18xx_rgu_setclear_reset(rcdev, id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int lpc18xx_rgu_status(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			      unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u32 bit, offset = LPC18XX_RGU_ACTIVE_STATUS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	bit = 1 << (id % LPC18XX_RGU_RESETS_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return !(readl(rc->base + offset) & bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct reset_control_ops lpc18xx_rgu_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.reset		= lpc18xx_rgu_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.assert		= lpc18xx_rgu_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.deassert	= lpc18xx_rgu_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.status		= lpc18xx_rgu_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int lpc18xx_rgu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct lpc18xx_rgu_data *rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	u32 fcclk, firc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	rc->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (IS_ERR(rc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return PTR_ERR(rc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	rc->clk_reg = devm_clk_get(&pdev->dev, "reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (IS_ERR(rc->clk_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		dev_err(&pdev->dev, "reg clock not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		return PTR_ERR(rc->clk_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	rc->clk_delay = devm_clk_get(&pdev->dev, "delay");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (IS_ERR(rc->clk_delay)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		dev_err(&pdev->dev, "delay clock not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		return PTR_ERR(rc->clk_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	ret = clk_prepare_enable(rc->clk_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		dev_err(&pdev->dev, "unable to enable reg clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	ret = clk_prepare_enable(rc->clk_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		dev_err(&pdev->dev, "unable to enable delay clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		goto dis_clk_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	fcclk = clk_get_rate(rc->clk_reg) / USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	firc = clk_get_rate(rc->clk_delay) / USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (fcclk == 0 || firc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		rc->delay_us = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		rc->delay_us = DIV_ROUND_UP(fcclk, firc * firc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	spin_lock_init(&rc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	rc->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	rc->rcdev.nr_resets = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	rc->rcdev.ops = &lpc18xx_rgu_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	rc->rcdev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	platform_set_drvdata(pdev, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	ret = reset_controller_register(&rc->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		dev_err(&pdev->dev, "unable to register device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		goto dis_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	rc->restart_nb.priority = 192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	rc->restart_nb.notifier_call = lpc18xx_rgu_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	ret = register_restart_handler(&rc->restart_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		dev_warn(&pdev->dev, "failed to register restart handler\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dis_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	clk_disable_unprepare(rc->clk_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dis_clk_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	clk_disable_unprepare(rc->clk_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct of_device_id lpc18xx_rgu_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	{ .compatible = "nxp,lpc1850-rgu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct platform_driver lpc18xx_rgu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.probe	= lpc18xx_rgu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		.name			= "lpc18xx-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		.of_match_table		= lpc18xx_rgu_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.suppress_bind_attrs	= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) builtin_platform_driver(lpc18xx_rgu_driver);