^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2010 John Crispin <blogic@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LANTIQ_RCU_RESET_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct lantiq_rcu_reset_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 reset_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 status_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static struct lantiq_rcu_reset_priv *to_lantiq_rcu_reset_priv(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct reset_controller_dev *rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return container_of(rcdev, struct lantiq_rcu_reset_priv, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int lantiq_rcu_reset_status(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int status = (id >> 8) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ret = regmap_read(priv->regmap, priv->status_offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return !!(val & BIT(status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int lantiq_rcu_reset_status_timeout(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long id, bool assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int retry = LANTIQ_RCU_RESET_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ret = lantiq_rcu_reset_status(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (ret == assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) usleep_range(20, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) } while (--retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int lantiq_rcu_reset_update(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long id, bool assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int set = id & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 val = assert ? BIT(set) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ret = regmap_update_bits(priv->regmap, priv->reset_offset, BIT(set),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dev_err(priv->dev, "Failed to set reset bit %u\n", set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = lantiq_rcu_reset_status_timeout(rcdev, id, assert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dev_err(priv->dev, "Failed to %s bit %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) assert ? "assert" : "deassert", set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int lantiq_rcu_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return lantiq_rcu_reset_update(rcdev, id, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int lantiq_rcu_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return lantiq_rcu_reset_update(rcdev, id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int lantiq_rcu_reset_reset(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ret = lantiq_rcu_reset_assert(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return lantiq_rcu_reset_deassert(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct reset_control_ops lantiq_rcu_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .assert = lantiq_rcu_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .deassert = lantiq_rcu_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .status = lantiq_rcu_reset_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .reset = lantiq_rcu_reset_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int lantiq_rcu_reset_of_parse(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct lantiq_rcu_reset_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const __be32 *offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) priv->regmap = syscon_node_to_regmap(dev->of_node->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (IS_ERR(priv->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) dev_err(&pdev->dev, "Failed to lookup RCU regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return PTR_ERR(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) offset = of_get_address(dev->of_node, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (!offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dev_err(&pdev->dev, "Failed to get RCU reset offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) priv->reset_offset = __be32_to_cpu(*offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) offset = of_get_address(dev->of_node, 1, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (!offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_err(&pdev->dev, "Failed to get RCU status offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) priv->status_offset = __be32_to_cpu(*offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int lantiq_rcu_reset_xlate(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const struct of_phandle_args *reset_spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned int status, set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) set = reset_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) status = reset_spec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (set >= rcdev->nr_resets || status >= rcdev->nr_resets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return (status << 8) | set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int lantiq_rcu_reset_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct lantiq_rcu_reset_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) err = lantiq_rcu_reset_of_parse(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) priv->rcdev.ops = &lantiq_rcu_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) priv->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) priv->rcdev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) priv->rcdev.nr_resets = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) priv->rcdev.of_xlate = lantiq_rcu_reset_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) priv->rcdev.of_reset_n_cells = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return reset_controller_register(&priv->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct of_device_id lantiq_rcu_reset_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { .compatible = "lantiq,danube-reset", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { .compatible = "lantiq,xrx200-reset", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MODULE_DEVICE_TABLE(of, lantiq_rcu_reset_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static struct platform_driver lantiq_rcu_reset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .probe = lantiq_rcu_reset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .name = "lantiq-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .of_match_table = lantiq_rcu_reset_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) module_platform_driver(lantiq_rcu_reset_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MODULE_DESCRIPTION("Lantiq XWAY RCU Reset Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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