^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017, Impinj, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * i.MX7 System Reset Controller (SRC) driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/reset/imx7-reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/reset/imx8mq-reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/reset/imx8mp-reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct imx7_src_signal {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned int offset, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct imx7_src_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) const struct imx7_src_signal *signals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned int signals_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct reset_control_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct imx7_src {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) const struct imx7_src_signal *signals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum imx7_src_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SRC_A7RCR0 = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SRC_M4RCR = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SRC_ERCR = 0x0014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SRC_HSICPHY_RCR = 0x001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SRC_USBOPHY1_RCR = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SRC_USBOPHY2_RCR = 0x0024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SRC_MIPIPHY_RCR = 0x0028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SRC_PCIEPHY_RCR = 0x002c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SRC_DDRC_RCR = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int imx7_reset_update(struct imx7_src *imx7src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long id, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const struct imx7_src_signal *signal = &imx7src->signals[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return regmap_update_bits(imx7src->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) signal->offset, signal->bit, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) [IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) [IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) [IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) [IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) [IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) [IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) [IMX7_RESET_EIM_RST] = { SRC_ERCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) [IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [IMX7_RESET_USBPHY1_POR] = { SRC_USBOPHY1_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) [IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) [IMX7_RESET_USBPHY2_POR] = { SRC_USBOPHY2_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) [IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) [IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) [IMX7_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) [IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [IMX7_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) [IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) [IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct imx7_src *to_imx7_src(struct reset_controller_dev *rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return container_of(rcdev, struct imx7_src, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int imx7_reset_set(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long id, bool assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct imx7_src *imx7src = to_imx7_src(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const unsigned int bit = imx7src->signals[id].bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int value = assert ? bit : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case IMX7_RESET_PCIEPHY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * wait for more than 10us to release phy g_rst and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * btnrst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (!assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case IMX7_RESET_PCIE_CTRL_APPS_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) value = assert ? 0 : bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return imx7_reset_update(imx7src, id, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int imx7_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return imx7_reset_set(rcdev, id, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int imx7_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return imx7_reset_set(rcdev, id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct imx7_src_variant variant_imx7 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .signals = imx7_src_signals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .signals_num = ARRAY_SIZE(imx7_src_signals),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .assert = imx7_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .deassert = imx7_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) enum imx8mq_src_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) SRC_A53RCR0 = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) SRC_HDMI_RCR = 0x0030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SRC_DISP_RCR = 0x0034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) SRC_GPU_RCR = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) SRC_VPU_RCR = 0x0044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) SRC_PCIE2_RCR = 0x0048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) SRC_MIPIPHY1_RCR = 0x004c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) SRC_MIPIPHY2_RCR = 0x0050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) SRC_DDRC2_RCR = 0x1004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) enum imx8mp_src_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) SRC_SUPERMIX_RCR = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) SRC_AUDIOMIX_RCR = 0x001c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) SRC_MLMIX_RCR = 0x0028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) SRC_GPU2D_RCR = 0x0038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SRC_GPU3D_RCR = 0x003c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) SRC_VPU_G1_RCR = 0x0048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) SRC_VPU_G2_RCR = 0x004c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) SRC_VPUVC8KE_RCR = 0x0050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) SRC_NOC_RCR = 0x0054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) [IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) [IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) [IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) [IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) [IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) [IMX8MQ_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [IMX8MQ_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [IMX8MQ_RESET_M4_ENABLE] = { SRC_M4RCR, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) BIT(2) | BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) [IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) [IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) [IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) [IMX8MQ_RESET_PCIEPHY2] = { SRC_PCIE2_RCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) BIT(2) | BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) [IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) [IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) [IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) [IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) [IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) [IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) [IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) [IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) [IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) [IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) [IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) [IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned long id, bool assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct imx7_src *imx7src = to_imx7_src(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) const unsigned int bit = imx7src->signals[id].bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int value = assert ? bit : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case IMX8MQ_RESET_PCIEPHY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) case IMX8MQ_RESET_PCIEPHY2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * wait for more than 10us to release phy g_rst and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * btnrst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case IMX8MQ_RESET_MIPI_DSI_RESET_N:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case IMX8MQ_RESET_M4_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) value = assert ? 0 : bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return imx7_reset_update(imx7src, id, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int imx8mq_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return imx8mq_reset_set(rcdev, id, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int imx8mq_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return imx8mq_reset_set(rcdev, id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const struct imx7_src_variant variant_imx8mq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .signals = imx8mq_src_signals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .signals_num = ARRAY_SIZE(imx8mq_src_signals),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .assert = imx8mq_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .deassert = imx8mq_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [IMX8MP_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) [IMX8MP_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) [IMX8MP_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) [IMX8MP_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [IMX8MP_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) [IMX8MP_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) [IMX8MP_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [IMX8MP_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [IMX8MP_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) [IMX8MP_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) [IMX8MP_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) [IMX8MP_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) [IMX8MP_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) [IMX8MP_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) [IMX8MP_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) [IMX8MP_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) [IMX8MP_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) [IMX8MP_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) [IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) [IMX8MP_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) [IMX8MP_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) [IMX8MP_RESET_SUPERMIX_RESET] = { SRC_SUPERMIX_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) [IMX8MP_RESET_AUDIOMIX_RESET] = { SRC_AUDIOMIX_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) [IMX8MP_RESET_MLMIX_RESET] = { SRC_MLMIX_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) [IMX8MP_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) [IMX8MP_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) [IMX8MP_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) [IMX8MP_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [IMX8MP_RESET_MEDIA_RESET] = { SRC_DISP_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) [IMX8MP_RESET_GPU2D_RESET] = { SRC_GPU2D_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) [IMX8MP_RESET_GPU3D_RESET] = { SRC_GPU3D_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) [IMX8MP_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) [IMX8MP_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) [IMX8MP_RESET_VPU_G1_RESET] = { SRC_VPU_G1_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) [IMX8MP_RESET_VPU_G2_RESET] = { SRC_VPU_G2_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) [IMX8MP_RESET_VPUVC8KE_RESET] = { SRC_VPUVC8KE_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) [IMX8MP_RESET_NOC_RESET] = { SRC_NOC_RCR, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int imx8mp_reset_set(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned long id, bool assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct imx7_src *imx7src = to_imx7_src(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) const unsigned int bit = imx7src->signals[id].bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned int value = assert ? bit : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case IMX8MP_RESET_PCIEPHY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * wait for more than 10us to release phy g_rst and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * btnrst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (!assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) value = assert ? 0 : bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return imx7_reset_update(imx7src, id, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int imx8mp_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return imx8mp_reset_set(rcdev, id, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int imx8mp_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return imx8mp_reset_set(rcdev, id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const struct imx7_src_variant variant_imx8mp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .signals = imx8mp_src_signals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .signals_num = ARRAY_SIZE(imx8mp_src_signals),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .assert = imx8mp_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .deassert = imx8mp_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int imx7_reset_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct imx7_src *imx7src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct regmap_config config = { .name = "src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) const struct imx7_src_variant *variant = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) imx7src = devm_kzalloc(dev, sizeof(*imx7src), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!imx7src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) imx7src->signals = variant->signals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) imx7src->regmap = syscon_node_to_regmap(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (IS_ERR(imx7src->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev_err(dev, "Unable to get imx7-src regmap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return PTR_ERR(imx7src->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) regmap_attach_dev(dev, imx7src->regmap, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) imx7src->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) imx7src->rcdev.nr_resets = variant->signals_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) imx7src->rcdev.ops = &variant->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) imx7src->rcdev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return devm_reset_controller_register(dev, &imx7src->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct of_device_id imx7_reset_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { .compatible = "fsl,imx7d-src", .data = &variant_imx7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { .compatible = "fsl,imx8mp-src", .data = &variant_imx8mp },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MODULE_DEVICE_TABLE(of, imx7_reset_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static struct platform_driver imx7_reset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .probe = imx7_reset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .of_match_table = imx7_reset_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) module_platform_driver(imx7_reset_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MODULE_AUTHOR("Andrey Smirnov <andrew.smirnov@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MODULE_DESCRIPTION("NXP i.MX7 reset driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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