^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2017 Synopsys.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Synopsys HSDK Development platform reset driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define to_hsdk_rst(p) container_of((p), struct hsdk_rst, rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct hsdk_rst {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void __iomem *regs_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void __iomem *regs_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static const u32 rst_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) BIT(16), /* APB_RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) BIT(17), /* AXI_RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) BIT(18), /* ETH_RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) BIT(19), /* USB_RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) BIT(20), /* SDIO_RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) BIT(21), /* HDMI_RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) BIT(22), /* GFX_RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) BIT(25), /* DMAC_RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) BIT(31), /* EBI_RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HSDK_MAX_RESETS ARRAY_SIZE(rst_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CGU_SYS_RST_CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CGU_IP_SW_RESET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CGU_IP_SW_RESET_DELAY_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CGU_IP_SW_RESET_DELAY_MASK GENMASK(31, CGU_IP_SW_RESET_DELAY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CGU_IP_SW_RESET_DELAY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CGU_IP_SW_RESET_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SW_RESET_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void hsdk_reset_config(struct hsdk_rst *rst, unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) writel(rst_map[id], rst->regs_ctl + CGU_SYS_RST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int hsdk_reset_do(struct hsdk_rst *rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) reg = readl(rst->regs_rst + CGU_IP_SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) reg &= ~CGU_IP_SW_RESET_DELAY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) reg |= CGU_IP_SW_RESET_DELAY << CGU_IP_SW_RESET_DELAY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) reg |= CGU_IP_SW_RESET_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) writel(reg, rst->regs_rst + CGU_IP_SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* wait till reset bit is back to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return readl_poll_timeout_atomic(rst->regs_rst + CGU_IP_SW_RESET, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) !(reg & CGU_IP_SW_RESET_RESET), 5, SW_RESET_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int hsdk_reset_reset(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct hsdk_rst *rst = to_hsdk_rst(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) spin_lock_irqsave(&rst->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) hsdk_reset_config(rst, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ret = hsdk_reset_do(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) spin_unlock_irqrestore(&rst->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const struct reset_control_ops hsdk_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .reset = hsdk_reset_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .deassert = hsdk_reset_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int hsdk_reset_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct hsdk_rst *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (!rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) rst->regs_ctl = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (IS_ERR(rst->regs_ctl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return PTR_ERR(rst->regs_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rst->regs_rst = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (IS_ERR(rst->regs_rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return PTR_ERR(rst->regs_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) spin_lock_init(&rst->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) rst->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) rst->rcdev.ops = &hsdk_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) rst->rcdev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) rst->rcdev.nr_resets = HSDK_MAX_RESETS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) rst->rcdev.of_reset_n_cells = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return reset_controller_register(&rst->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct of_device_id hsdk_reset_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { .compatible = "snps,hsdk-reset" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct platform_driver hsdk_reset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .probe = hsdk_reset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .name = "hsdk-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .of_match_table = hsdk_reset_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) builtin_platform_driver(hsdk_reset_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MODULE_AUTHOR("Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MODULE_DESCRIPTION("Synopsys HSDK SDP reset driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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