^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Broadcom STB generic reset controller for SW_INIT style reset controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Florian Fainelli <f.fainelli@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2018 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct brcmstb_reset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SW_INIT_SET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SW_INIT_CLEAR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SW_INIT_STATUS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SW_INIT_BIT(id) BIT((id) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SW_INIT_BANK(id) ((id) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* A full bank contains extra registers that we are not utilizing but still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * qualify as a single bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SW_INIT_BANK_SIZE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct brcmstb_reset *to_brcmstb(struct reset_controller_dev *rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return container_of(rcdev, struct brcmstb_reset, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int brcmstb_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct brcmstb_reset *priv = to_brcmstb(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int brcmstb_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct brcmstb_reset *priv = to_brcmstb(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Maximum reset delay after de-asserting a line and seeing block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * operation is typically 14us for the worst case, build some slack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int brcmstb_reset_status(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct brcmstb_reset *priv = to_brcmstb(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return readl_relaxed(priv->base + off + SW_INIT_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SW_INIT_BIT(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const struct reset_control_ops brcmstb_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .assert = brcmstb_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .deassert = brcmstb_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .status = brcmstb_reset_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int brcmstb_reset_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct device *kdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct brcmstb_reset *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) priv->base = devm_ioremap_resource(kdev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dev_set_drvdata(kdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) priv->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) priv->rcdev.nr_resets = DIV_ROUND_DOWN_ULL(resource_size(res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SW_INIT_BANK_SIZE) * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) priv->rcdev.ops = &brcmstb_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) priv->rcdev.of_node = kdev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Use defaults: 1 cell and simple xlate function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return devm_reset_controller_register(kdev, &priv->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const struct of_device_id brcmstb_reset_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { .compatible = "brcm,brcmstb-reset" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MODULE_DEVICE_TABLE(of, brcmstb_reset_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct platform_driver brcmstb_reset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .probe = brcmstb_reset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .name = "brcmstb-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .of_match_table = brcmstb_reset_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) module_platform_driver(brcmstb_reset_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MODULE_AUTHOR("Broadcom");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MODULE_DESCRIPTION("Broadcom STB reset controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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