^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AR71xx Reset Controller Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Alban Bedel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2015 Alban Bedel <albeu@free.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct ath79_reset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct notifier_block restart_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FULL_CHIP_RESET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int ath79_reset_update(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned long id, bool assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct ath79_reset *ath79_reset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) container_of(rcdev, struct ath79_reset, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) spin_lock_irqsave(&ath79_reset->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) val = readl(ath79_reset->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) val |= BIT(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) val &= ~BIT(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) writel(val, ath79_reset->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) spin_unlock_irqrestore(&ath79_reset->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int ath79_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return ath79_reset_update(rcdev, id, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int ath79_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return ath79_reset_update(rcdev, id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int ath79_reset_status(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct ath79_reset *ath79_reset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) container_of(rcdev, struct ath79_reset, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) val = readl(ath79_reset->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return !!(val & BIT(id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const struct reset_control_ops ath79_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .assert = ath79_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .deassert = ath79_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .status = ath79_reset_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int ath79_reset_restart_handler(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct ath79_reset *ath79_reset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) container_of(nb, struct ath79_reset, restart_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ath79_reset_assert(&ath79_reset->rcdev, FULL_CHIP_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int ath79_reset_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct ath79_reset *ath79_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ath79_reset = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) sizeof(*ath79_reset), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!ath79_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) platform_set_drvdata(pdev, ath79_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ath79_reset->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (IS_ERR(ath79_reset->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return PTR_ERR(ath79_reset->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) spin_lock_init(&ath79_reset->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ath79_reset->rcdev.ops = &ath79_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ath79_reset->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ath79_reset->rcdev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ath79_reset->rcdev.of_reset_n_cells = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ath79_reset->rcdev.nr_resets = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) err = devm_reset_controller_register(&pdev->dev, &ath79_reset->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ath79_reset->restart_nb.notifier_call = ath79_reset_restart_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ath79_reset->restart_nb.priority = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) err = register_restart_handler(&ath79_reset->restart_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_warn(&pdev->dev, "Failed to register restart handler\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct of_device_id ath79_reset_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { .compatible = "qca,ar7100-reset", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct platform_driver ath79_reset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .probe = ath79_reset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .name = "ath79-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .of_match_table = ath79_reset_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) builtin_platform_driver(ath79_reset_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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