^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright Intel Corporation (C) 2017. All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Reset driver for Altera Arria10 MAX5 System Resource Chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Adapted from reset-socfpga.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/altera-a10sr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/reset/altr,rst-mgr-a10sr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct a10sr_reset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static inline struct a10sr_reset *to_a10sr_rst(struct reset_controller_dev *rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) return container_of(rc, struct a10sr_reset, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static inline int a10sr_reset_shift(unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) case A10SR_RESET_ENET_HPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) case A10SR_RESET_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) case A10SR_RESET_FILE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) case A10SR_RESET_BQSPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) case A10SR_RESET_USB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return id + 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int a10sr_reset_update(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long id, bool assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct a10sr_reset *a10r = to_a10sr_rst(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int offset = a10sr_reset_shift(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 mask = ALTR_A10SR_REG_BIT_MASK(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int index = ALTR_A10SR_HPS_RST_REG + ALTR_A10SR_REG_OFFSET(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return regmap_update_bits(a10r->regmap, index, mask, assert ? 0 : mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int a10sr_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return a10sr_reset_update(rcdev, id, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int a10sr_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return a10sr_reset_update(rcdev, id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int a10sr_reset_status(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct a10sr_reset *a10r = to_a10sr_rst(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int offset = a10sr_reset_shift(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 mask = ALTR_A10SR_REG_BIT_MASK(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int index = ALTR_A10SR_HPS_RST_REG + ALTR_A10SR_REG_OFFSET(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ret = regmap_read(a10r->regmap, index, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return !!(value & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const struct reset_control_ops a10sr_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .assert = a10sr_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .deassert = a10sr_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .status = a10sr_reset_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int a10sr_reset_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct a10sr_reset *a10r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) a10r = devm_kzalloc(&pdev->dev, sizeof(struct a10sr_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (!a10r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) a10r->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) a10r->rcdev.nr_resets = A10SR_RESET_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) a10r->rcdev.ops = &a10sr_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) a10r->rcdev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) a10r->regmap = a10sr->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) platform_set_drvdata(pdev, a10r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return devm_reset_controller_register(&pdev->dev, &a10r->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct of_device_id a10sr_reset_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { .compatible = "altr,a10sr-reset" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MODULE_DEVICE_TABLE(of, a10sr_reset_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct platform_driver a10sr_reset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .probe = a10sr_reset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .name = "altr_a10sr_reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .of_match_table = a10sr_reset_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) module_platform_driver(a10sr_reset_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MODULE_AUTHOR("Thor Thayer <thor.thayer@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MODULE_DESCRIPTION("Altera Arria10 System Resource Reset Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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