^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Hisilicon Hi6220 reset controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 Linaro Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2015-2016 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Feng Chen <puck.chen@hisilicon.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PERIPH_ASSERT_OFFSET 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PERIPH_DEASSERT_OFFSET 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PERIPH_MAX_INDEX 0x509
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SC_MEDIA_RSTEN 0x052C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SC_MEDIA_RSTDIS 0x0530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MEDIA_MAX_INDEX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define to_reset_data(x) container_of(x, struct hi6220_reset_data, rc_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) enum hi6220_reset_ctrl_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PERIPHERAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MEDIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) AO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct hi6220_reset_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct reset_controller_dev rc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int hi6220_peripheral_assert(struct reset_controller_dev *rc_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct hi6220_reset_data *data = to_reset_data(rc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct regmap *regmap = data->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 bank = idx >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 offset = idx & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 reg = PERIPH_ASSERT_OFFSET + bank * 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return regmap_write(regmap, reg, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int hi6220_peripheral_deassert(struct reset_controller_dev *rc_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct hi6220_reset_data *data = to_reset_data(rc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct regmap *regmap = data->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 bank = idx >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 offset = idx & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 reg = PERIPH_DEASSERT_OFFSET + bank * 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return regmap_write(regmap, reg, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const struct reset_control_ops hi6220_peripheral_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .assert = hi6220_peripheral_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .deassert = hi6220_peripheral_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int hi6220_media_assert(struct reset_controller_dev *rc_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct hi6220_reset_data *data = to_reset_data(rc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct regmap *regmap = data->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return regmap_write(regmap, SC_MEDIA_RSTEN, BIT(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int hi6220_media_deassert(struct reset_controller_dev *rc_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct hi6220_reset_data *data = to_reset_data(rc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct regmap *regmap = data->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return regmap_write(regmap, SC_MEDIA_RSTDIS, BIT(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct reset_control_ops hi6220_media_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .assert = hi6220_media_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .deassert = hi6220_media_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AO_SCTRL_SC_PW_CLKEN0 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AO_SCTRL_SC_PW_CLKDIS0 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AO_SCTRL_SC_PW_RSTEN0 0x810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AO_SCTRL_SC_PW_RSTDIS0 0x814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AO_SCTRL_SC_PW_ISOEN0 0x820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AO_SCTRL_SC_PW_ISODIS0 0x824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AO_MAX_INDEX 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int hi6220_ao_assert(struct reset_controller_dev *rc_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned long idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct hi6220_reset_data *data = to_reset_data(rc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct regmap *regmap = data->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTEN0, BIT(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ret = regmap_write(regmap, AO_SCTRL_SC_PW_ISOEN0, BIT(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ret = regmap_write(regmap, AO_SCTRL_SC_PW_CLKDIS0, BIT(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int hi6220_ao_deassert(struct reset_controller_dev *rc_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned long idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct hi6220_reset_data *data = to_reset_data(rc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct regmap *regmap = data->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * It was suggested to disable isolation before enabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * the clocks and deasserting reset, to avoid glitches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * But this order is preserved to keep it matching the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * vendor code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTDIS0, BIT(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ret = regmap_write(regmap, AO_SCTRL_SC_PW_ISODIS0, BIT(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = regmap_write(regmap, AO_SCTRL_SC_PW_CLKEN0, BIT(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct reset_control_ops hi6220_ao_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .assert = hi6220_ao_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .deassert = hi6220_ao_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int hi6220_reset_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) enum hi6220_reset_ctrl_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct hi6220_reset_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) type = (enum hi6220_reset_ctrl_type)of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) regmap = syscon_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dev_err(dev, "failed to get reset controller regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) data->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) data->rc_dev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (type == MEDIA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) data->rc_dev.ops = &hi6220_media_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) data->rc_dev.nr_resets = MEDIA_MAX_INDEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) } else if (type == PERIPHERAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) data->rc_dev.ops = &hi6220_peripheral_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) data->rc_dev.nr_resets = PERIPH_MAX_INDEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) data->rc_dev.ops = &hi6220_ao_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) data->rc_dev.nr_resets = AO_MAX_INDEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return reset_controller_register(&data->rc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct of_device_id hi6220_reset_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .compatible = "hisilicon,hi6220-sysctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .data = (void *)PERIPHERAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .compatible = "hisilicon,hi6220-mediactrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .data = (void *)MEDIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .compatible = "hisilicon,hi6220-aoctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .data = (void *)AO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MODULE_DEVICE_TABLE(of, hi6220_reset_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct platform_driver hi6220_reset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .probe = hi6220_reset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = "reset-hi6220",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .of_match_table = hi6220_reset_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int __init hi6220_reset_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return platform_driver_register(&hi6220_reset_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) postcore_initcall(hi6220_reset_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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