Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) config ARCH_HAS_RESET_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) menuconfig RESET_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 	bool "Reset Controller Support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 	default y if ARCH_HAS_RESET_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 	  Generic Reset Controller support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 	  This framework is designed to abstract reset handling of devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	  via GPIOs or SoC-internal reset controller modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	  If unsure, say no.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) if RESET_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) config RESET_A10SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	tristate "Altera Arria10 System Resource Reset"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	depends on MFD_ALTERA_A10SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	  This option enables support for the external reset functions for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	  peripheral PHYs on the Altera Arria10 System Resource Chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) config RESET_ATH79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	bool "AR71xx Reset Driver" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	default ATH79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	  This enables the ATH79 reset controller driver that supports the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	  AR71xx SoC reset controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) config RESET_AXS10X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	bool "AXS10x Reset Driver" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	default ARC_PLAT_AXS10X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	  This enables the reset controller driver for AXS10x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) config RESET_BERLIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	bool "Berlin Reset Driver" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	default ARCH_BERLIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	  This enables the reset controller driver for Marvell Berlin SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) config RESET_BRCMSTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	tristate "Broadcom STB reset controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	depends on ARCH_BRCMSTB || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	default ARCH_BRCMSTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	  This enables the reset controller driver for Broadcom STB SoCs using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	  a SUN_TOP_CTRL_SW_INIT style controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) config RESET_BRCMSTB_RESCAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	bool "Broadcom STB RESCAL reset controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	depends on ARCH_BRCMSTB || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	default ARCH_BRCMSTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	  This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	  BCM7216.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) config RESET_HSDK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	bool "Synopsys HSDK Reset Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	depends on ARC_SOC_HSDK || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	  This enables the reset controller driver for HSDK board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) config RESET_IMX7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	tristate "i.MX7/8 Reset Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	default y if SOC_IMX7D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	select MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	  This enables the reset controller driver for i.MX7 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) config RESET_INTEL_GW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	bool "Intel Reset Controller Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	depends on X86 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	depends on OF && HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	select REGMAP_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	  This enables the reset controller driver for Intel Gateway SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	  Say Y to control the reset signals provided by reset controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	  Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) config RESET_LANTIQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	default SOC_TYPE_XWAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	  This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) config RESET_LPC18XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	default ARCH_LPC18XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	  This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) config RESET_MESON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	tristate "Meson Reset Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	depends on ARCH_MESON || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	default ARCH_MESON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	  This enables the reset driver for Amlogic Meson SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) config RESET_MESON_AUDIO_ARB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	tristate "Meson Audio Memory Arbiter Reset Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	depends on ARCH_MESON || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	  This enables the reset driver for Audio Memory Arbiter of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	  Amlogic's A113 based SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) config RESET_NPCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	bool "NPCM BMC Reset Driver" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	default ARCH_NPCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	  This enables the reset controller driver for Nuvoton NPCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	  BMC SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) config RESET_OXNAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) config RESET_PISTACHIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	bool "Pistachio Reset Driver" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	default MACH_PISTACHIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	  This enables the reset driver for ImgTec Pistachio SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) config RESET_QCOM_AOSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	tristate "Qcom AOSS Reset Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	depends on ARCH_QCOM || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	  This enables the AOSS (always on subsystem) reset driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	  for Qualcomm SDM845 SoCs. Say Y if you want to control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	  reset signals provided by AOSS for Modem, Venus, ADSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	  GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) config RESET_QCOM_PDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	tristate "Qualcomm PDC Reset Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	depends on ARCH_QCOM || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	  This enables the PDC (Power Domain Controller) reset driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	  for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	  to control reset signals provided by PDC for Modem, Compute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	  Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) config RESET_RASPBERRYPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	tristate "Raspberry Pi 4 Firmware Reset Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	default USB_XHCI_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	  Raspberry Pi 4's co-processor controls some of the board's HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	  initialization process, but it's up to Linux to trigger it when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	  relevant. This driver provides a reset controller capable of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	  interfacing with RPi4's co-processor and model these firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	  initialization routines as reset lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) config RESET_SCMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	tristate "Reset driver controlled via ARM SCMI interface"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	default ARM_SCMI_PROTOCOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	  This driver provides support for reset signal/domains that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	  controlled by firmware that implements the SCMI interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	  This driver uses SCMI Message Protocol to interact with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	  firmware controlling all the reset signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) config RESET_SIMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	bool "Simple Reset Controller Driver" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	  This enables a simple reset controller driver for reset lines that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	  that can be asserted and deasserted by toggling bits in a contiguous,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	  exclusive register space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	  Currently this driver supports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	   - Altera SoCFPGAs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	   - ASPEED BMC SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	   - Bitmain BM1880 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	   - Realtek SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	   - RCC reset controller in STM32 MCUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	   - Allwinner SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	   - ZTE's zx2967 family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) config RESET_STM32MP157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	bool "STM32MP157 Reset Driver" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	default MACH_STM32MP157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	  This enables the RCC reset controller driver for STM32 MPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) config RESET_SOCFPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	default ARCH_SOCFPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	select RESET_SIMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	  driver gets initialized early during platform init calls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) config RESET_SUNXI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	default ARCH_SUNXI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	select RESET_SIMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	  This enables the reset driver for Allwinner SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) config RESET_TI_SCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	tristate "TI System Control Interface (TI-SCI) reset driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	depends on TI_SCI_PROTOCOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	  This enables the reset driver support over TI System Control Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	  available on some new TI's SoCs. If you wish to use reset resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	  managed by the TI System Controller, say Y here. Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) config RESET_TI_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	tristate "TI SYSCON Reset Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	select MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	  This enables the reset driver support for TI devices with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	  memory-mapped reset registers as part of a syscon device node. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	  you wish to use the reset framework for such memory-mapped devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	  say Y here. Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) config RESET_UNIPHIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	tristate "Reset controller driver for UniPhier SoCs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	depends on ARCH_UNIPHIER || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	depends on OF && MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	default ARCH_UNIPHIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	  Support for reset controllers on UniPhier SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	  Say Y if you want to control reset signals provided by System Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	  block, Media I/O block, Peripheral Block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) config RESET_UNIPHIER_GLUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	tristate "Reset driver in glue layer for UniPhier SoCs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	default ARCH_UNIPHIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	select RESET_SIMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	  Support for peripheral core reset included in its own glue layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	  on UniPhier SoCs. Say Y if you want to control reset signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	  provided by the glue layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) config RESET_ZYNQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	bool "ZYNQ Reset Driver" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	default ARCH_ZYNQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	  This enables the reset controller driver for Xilinx Zynq SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) source "drivers/reset/sti/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) source "drivers/reset/hisilicon/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) source "drivers/reset/tegra/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) endif