^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Qualcomm Wireless Connectivity Subsystem Iris driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Linaro Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014 Sony Mobile Communications AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "qcom_wcnss.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct qcom_iris {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk *xo_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct regulator_bulk_data *vregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) size_t num_vregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct iris_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) const struct wcnss_vreg_info *vregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) size_t num_vregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) bool use_48mhz_xo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct iris_data wcn3620_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .vregs = (struct wcnss_vreg_info[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { "vddxo", 1800000, 1800000, 10000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { "vddrfa", 1300000, 1300000, 100000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { "vddpa", 3300000, 3300000, 515000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { "vdddig", 1800000, 1800000, 10000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .num_vregs = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .use_48mhz_xo = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const struct iris_data wcn3660_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .vregs = (struct wcnss_vreg_info[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { "vddxo", 1800000, 1800000, 10000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { "vddrfa", 1300000, 1300000, 100000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { "vddpa", 2900000, 3000000, 515000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { "vdddig", 1200000, 1225000, 10000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .num_vregs = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .use_48mhz_xo = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct iris_data wcn3680_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .vregs = (struct wcnss_vreg_info[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { "vddxo", 1800000, 1800000, 10000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { "vddrfa", 1300000, 1300000, 100000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { "vddpa", 3300000, 3300000, 515000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { "vdddig", 1800000, 1800000, 10000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .num_vregs = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .use_48mhz_xo = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int qcom_iris_enable(struct qcom_iris *iris)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ret = regulator_bulk_enable(iris->num_vregs, iris->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ret = clk_prepare_enable(iris->xo_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dev_err(iris->dev, "failed to enable xo clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) goto disable_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) disable_regulators:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) regulator_bulk_disable(iris->num_vregs, iris->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void qcom_iris_disable(struct qcom_iris *iris)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clk_disable_unprepare(iris->xo_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) regulator_bulk_disable(iris->num_vregs, iris->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int qcom_iris_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const struct iris_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct qcom_wcnss *wcnss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct qcom_iris *iris;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) iris = devm_kzalloc(&pdev->dev, sizeof(struct qcom_iris), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (!iris)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) wcnss = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) iris->xo_clk = devm_clk_get(&pdev->dev, "xo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (IS_ERR(iris->xo_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (PTR_ERR(iris->xo_clk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dev_err(&pdev->dev, "failed to acquire xo clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return PTR_ERR(iris->xo_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) iris->num_vregs = data->num_vregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) iris->vregs = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) iris->num_vregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) sizeof(struct regulator_bulk_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (!iris->vregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) for (i = 0; i < iris->num_vregs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) iris->vregs[i].supply = data->vregs[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = devm_regulator_bulk_get(&pdev->dev, iris->num_vregs, iris->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) dev_err(&pdev->dev, "failed to get regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) for (i = 0; i < iris->num_vregs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (data->vregs[i].max_voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) regulator_set_voltage(iris->vregs[i].consumer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) data->vregs[i].min_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) data->vregs[i].max_voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (data->vregs[i].load_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) regulator_set_load(iris->vregs[i].consumer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) data->vregs[i].load_uA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) qcom_wcnss_assign_iris(wcnss, iris, data->use_48mhz_xo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int qcom_iris_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct qcom_wcnss *wcnss = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) qcom_wcnss_assign_iris(wcnss, NULL, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct of_device_id iris_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { .compatible = "qcom,wcn3620", .data = &wcn3620_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { .compatible = "qcom,wcn3660", .data = &wcn3660_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { .compatible = "qcom,wcn3680", .data = &wcn3680_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MODULE_DEVICE_TABLE(of, iris_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct platform_driver qcom_iris_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .probe = qcom_iris_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .remove = qcom_iris_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .name = "qcom-iris",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .of_match_table = iris_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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