^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Linaro Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014 Sony Mobile Communications AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/qcom_scm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/remoteproc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/soc/qcom/mdt_loader.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/soc/qcom/smem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/soc/qcom/smem_state.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/rpmsg/qcom_smd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "qcom_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "remoteproc_internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "qcom_pil_info.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "qcom_wcnss.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define WCNSS_CRASH_REASON_SMEM 422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define WCNSS_FIRMWARE_NAME "wcnss.mdt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define WCNSS_PAS_ID 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WCNSS_SSCTL_ID 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define WCNSS_SPARE_NVBIN_DLND BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define WCNSS_PMU_IRIS_XO_CFG BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define WCNSS_PMU_IRIS_XO_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WCNSS_PMU_GC_BUS_MUX_SEL_TOP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define WCNSS_PMU_IRIS_RESET BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define WCNSS_PMU_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define WCNSS_PMU_IRIS_XO_READ BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define WCNSS_PMU_IRIS_XO_READ_STS BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define WCNSS_PMU_XO_MODE_MASK GENMASK(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define WCNSS_PMU_XO_MODE_19p2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define WCNSS_PMU_XO_MODE_48 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct wcnss_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) size_t pmu_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) size_t spare_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const struct wcnss_vreg_info *vregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) size_t num_vregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct qcom_wcnss {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct rproc *rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void __iomem *pmu_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void __iomem *spare_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) bool use_48mhz_xo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int wdog_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int fatal_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int ready_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int handover_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int stop_ack_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct qcom_smem_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned stop_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct mutex iris_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct qcom_iris *iris;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct regulator_bulk_data *vregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) size_t num_vregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct completion start_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct completion stop_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) phys_addr_t mem_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) phys_addr_t mem_reloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void *mem_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) size_t mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct qcom_rproc_subdev smd_subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct qcom_sysmon *sysmon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const struct wcnss_data riva_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .pmu_offset = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .spare_offset = 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .vregs = (struct wcnss_vreg_info[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { "vddmx", 1050000, 1150000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { "vddcx", 1050000, 1150000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { "vddpx", 1800000, 1800000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .num_vregs = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const struct wcnss_data pronto_v1_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .pmu_offset = 0x1004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .spare_offset = 0x1088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .vregs = (struct wcnss_vreg_info[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { "vddmx", 950000, 1150000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { "vddcx", .super_turbo = true},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { "vddpx", 1800000, 1800000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .num_vregs = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct wcnss_data pronto_v2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .pmu_offset = 0x1004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .spare_offset = 0x1088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .vregs = (struct wcnss_vreg_info[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { "vddmx", 1287500, 1287500, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { "vddcx", .super_turbo = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { "vddpx", 1800000, 1800000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .num_vregs = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct qcom_iris *iris,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bool use_48mhz_xo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mutex_lock(&wcnss->iris_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) wcnss->iris = iris;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) wcnss->use_48mhz_xo = use_48mhz_xo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mutex_unlock(&wcnss->iris_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) wcnss->mem_region, wcnss->mem_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) wcnss->mem_size, &wcnss->mem_reloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) qcom_pil_info_store("wcnss", wcnss->mem_phys, wcnss->mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Indicate NV download capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val = readl(wcnss->spare_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) val |= WCNSS_SPARE_NVBIN_DLND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writel(val, wcnss->spare_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void wcnss_configure_iris(struct qcom_wcnss *wcnss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Clear PMU cfg register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) writel(0, wcnss->pmu_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) writel(val, wcnss->pmu_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Clear XO_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) val &= ~WCNSS_PMU_XO_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (wcnss->use_48mhz_xo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) val |= WCNSS_PMU_XO_MODE_48 << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val |= WCNSS_PMU_XO_MODE_19p2 << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel(val, wcnss->pmu_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Reset IRIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val |= WCNSS_PMU_IRIS_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) writel(val, wcnss->pmu_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Wait for PMU.iris_reg_reset_sts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Clear IRIS reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) val &= ~WCNSS_PMU_IRIS_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) writel(val, wcnss->pmu_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Start IRIS XO configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) val |= WCNSS_PMU_IRIS_XO_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writel(val, wcnss->pmu_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Wait for XO configuration to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Stop IRIS XO configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) val &= ~WCNSS_PMU_IRIS_XO_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) writel(val, wcnss->pmu_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Add some delay for XO to settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int wcnss_start(struct rproc *rproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mutex_lock(&wcnss->iris_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!wcnss->iris) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_err(wcnss->dev, "no iris registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) goto release_iris_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto release_iris_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = qcom_iris_enable(wcnss->iris);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) goto disable_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) wcnss_indicate_nv_download(wcnss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) wcnss_configure_iris(wcnss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_err(wcnss->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "failed to authenticate image and release reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto disable_iris;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = wait_for_completion_timeout(&wcnss->start_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) msecs_to_jiffies(5000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (wcnss->ready_irq > 0 && ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* We have a ready_irq, but it didn't fire in time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dev_err(wcnss->dev, "start timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) qcom_scm_pas_shutdown(WCNSS_PAS_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) goto disable_iris;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) disable_iris:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) qcom_iris_disable(wcnss->iris);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) disable_regulators:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) release_iris_lock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mutex_unlock(&wcnss->iris_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int wcnss_stop(struct rproc *rproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (wcnss->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) qcom_smem_state_update_bits(wcnss->state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) BIT(wcnss->stop_bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) BIT(wcnss->stop_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ret = wait_for_completion_timeout(&wcnss->stop_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) msecs_to_jiffies(5000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dev_err(wcnss->dev, "timed out on wait\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) qcom_smem_state_update_bits(wcnss->state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) BIT(wcnss->stop_bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_err(wcnss->dev, "failed to shutdown: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void *wcnss_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) offset = da - wcnss->mem_reloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (offset < 0 || offset + len > wcnss->mem_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return wcnss->mem_region + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const struct rproc_ops wcnss_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .start = wcnss_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .stop = wcnss_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .da_to_va = wcnss_da_to_va,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .parse_fw = qcom_register_dump_segments,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .load = wcnss_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct qcom_wcnss *wcnss = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct qcom_wcnss *wcnss = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) char *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!IS_ERR(msg) && len > 0 && msg[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev_err(wcnss->dev, "fatal error received: %s\n", msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static irqreturn_t wcnss_ready_interrupt(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct qcom_wcnss *wcnss = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) complete(&wcnss->start_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static irqreturn_t wcnss_handover_interrupt(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * XXX: At this point we're supposed to release the resources that we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * have been holding on behalf of the WCNSS. Unfortunately this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * interrupt comes way before the other side seems to be done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * So we're currently relying on the ready interrupt firing later then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * this and we just disable the resources at the end of wcnss_start().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct qcom_wcnss *wcnss = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) complete(&wcnss->stop_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int wcnss_init_regulators(struct qcom_wcnss *wcnss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) const struct wcnss_vreg_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int num_vregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct regulator_bulk_data *bulk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) bulk = devm_kcalloc(wcnss->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) num_vregs, sizeof(struct regulator_bulk_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (!bulk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) for (i = 0; i < num_vregs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) bulk[i].supply = info[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) for (i = 0; i < num_vregs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (info[i].max_voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) regulator_set_voltage(bulk[i].consumer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) info[i].min_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) info[i].max_voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (info[i].load_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) regulator_set_load(bulk[i].consumer, info[i].load_uA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) wcnss->vregs = bulk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) wcnss->num_vregs = num_vregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int wcnss_request_irq(struct qcom_wcnss *wcnss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) bool optional,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) irq_handler_t thread_fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = platform_get_irq_byname(pdev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (ret < 0 && optional) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) } else if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_err(&pdev->dev, "no %s IRQ defined\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = devm_request_threaded_irq(&pdev->dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) NULL, thread_fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) IRQF_TRIGGER_RISING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "wcnss", wcnss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_err(&pdev->dev, "request %s IRQ failed\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct resource r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(wcnss->dev, "no memory-region specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = of_address_to_resource(node, 0, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) wcnss->mem_phys = wcnss->mem_reloc = r.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) wcnss->mem_size = resource_size(&r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (!wcnss->mem_region) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) &r.start, wcnss->mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int wcnss_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) const struct wcnss_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct qcom_wcnss *wcnss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct rproc *rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (!qcom_scm_is_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev_err(&pdev->dev, "PAS is not available for WCNSS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) WCNSS_FIRMWARE_NAME, sizeof(*wcnss));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (!rproc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_err(&pdev->dev, "unable to allocate remoteproc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) wcnss = (struct qcom_wcnss *)rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) wcnss->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) wcnss->rproc = rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) platform_set_drvdata(pdev, wcnss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) init_completion(&wcnss->start_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) init_completion(&wcnss->stop_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mutex_init(&wcnss->iris_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) mmio = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (IS_ERR(mmio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = PTR_ERR(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ret = wcnss_alloc_memory_region(wcnss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) wcnss->pmu_cfg = mmio + data->pmu_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) wcnss->spare_out = mmio + data->spare_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) wcnss->wdog_irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) wcnss->fatal_irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) wcnss->ready_irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) wcnss->handover_irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) wcnss->stop_ack_irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (wcnss->stop_ack_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) wcnss->state = qcom_smem_state_get(&pdev->dev, "stop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) &wcnss->stop_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (IS_ERR(wcnss->state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ret = PTR_ERR(wcnss->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) qcom_add_smd_subdev(rproc, &wcnss->smd_subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) wcnss->sysmon = qcom_add_sysmon_subdev(rproc, "wcnss", WCNSS_SSCTL_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (IS_ERR(wcnss->sysmon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = PTR_ERR(wcnss->sysmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = rproc_add(rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) free_rproc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) rproc_free(rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int wcnss_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct qcom_wcnss *wcnss = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) of_platform_depopulate(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) qcom_smem_state_put(wcnss->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) rproc_del(wcnss->rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) qcom_remove_sysmon_subdev(wcnss->sysmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) qcom_remove_smd_subdev(wcnss->rproc, &wcnss->smd_subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) rproc_free(wcnss->rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const struct of_device_id wcnss_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) { .compatible = "qcom,riva-pil", &riva_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) { .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) { .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MODULE_DEVICE_TABLE(of, wcnss_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static struct platform_driver wcnss_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .probe = wcnss_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .remove = wcnss_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .name = "qcom-wcnss-pil",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .of_match_table = wcnss_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int __init wcnss_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = platform_driver_register(&wcnss_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ret = platform_driver_register(&qcom_iris_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) platform_driver_unregister(&wcnss_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) module_init(wcnss_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static void __exit wcnss_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) platform_driver_unregister(&qcom_iris_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) platform_driver_unregister(&wcnss_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) module_exit(wcnss_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Wireless Subsystem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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