^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Qualcomm self-authenticating modem subsystem remoteproc driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014 Sony Mobile Communications AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/devcoredump.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/remoteproc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/soc/qcom/mdt_loader.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "remoteproc_internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "qcom_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "qcom_pil_info.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "qcom_q6v5.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/qcom_scm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MPSS_CRASH_REASON_SMEM 421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MBA_LOG_SIZE SZ_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* RMB Status Register Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RMB_PBL_SUCCESS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RMB_MBA_XPU_UNLOCKED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RMB_MBA_AUTH_COMPLETE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* PBL/MBA interface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RMB_MBA_IMAGE_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RMB_PBL_STATUS_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RMB_MBA_COMMAND_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RMB_MBA_STATUS_REG 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RMB_PMI_META_DATA_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RMB_PMI_CODE_START_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RMB_PMI_CODE_LENGTH_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RMB_MBA_MSS_STATUS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RMB_MBA_ALT_RESET 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RMB_CMD_META_DATA_READY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RMB_CMD_LOAD_READY 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* QDSP6SS Register Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define QDSP6SS_RESET_REG 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define QDSP6SS_GFMUX_CTL_REG 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define QDSP6SS_PWR_CTL_REG 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define QDSP6SS_MEM_PWR_CTL 0x0B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define QDSP6V6SS_MEM_PWR_CTL 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define QDSP6SS_STRAP_ACC 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* AXI Halt Register Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AXI_HALTREQ_REG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AXI_HALTACK_REG 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AXI_IDLE_REG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AXI_GATING_VALID_OVERRIDE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HALT_ACK_TIMEOUT_US 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* QDSP6SS_RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define Q6SS_STOP_CORE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define Q6SS_CORE_ARES BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define Q6SS_BUS_ARES_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* QDSP6SS CBCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define Q6SS_CBCR_CLKEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define Q6SS_CBCR_CLKOFF BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define Q6SS_CBCR_TIMEOUT_US 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* QDSP6SS_GFMUX_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define Q6SS_CLK_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* QDSP6SS_PWR_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define Q6SS_L2TAG_SLP_NRET_N BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define Q6SS_ETB_SLP_NRET_N BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define Q6SS_L2DATA_STBY_N BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define Q6SS_SLP_RET_N BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define Q6SS_CLAMP_IO BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define QDSS_BHS_ON BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define QDSS_LDO_BYP BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* QDSP6v56 parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define QDSP6v56_LDO_BYP BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define QDSP6v56_BHS_ON BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define QDSP6v56_CLAMP_WL BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define QDSP6v56_CLAMP_QMC_MEM BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define QDSP6SS_XO_CBCR 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define QDSP6SS_ACC_OVERRIDE_VAL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* QDSP6v65 parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define QDSP6SS_CORE_CBCR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define QDSP6SS_SLEEP 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define QDSP6SS_BOOT_CORE_START 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define QDSP6SS_BOOT_CMD 0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BOOT_FSM_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct reg_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct qcom_mss_reg_res {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const char *supply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct rproc_hexagon_res {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const char *hexagon_mba_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct qcom_mss_reg_res *proxy_supply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct qcom_mss_reg_res *active_supply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) char **proxy_clk_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) char **reset_clk_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) char **active_clk_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) char **active_pd_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) char **proxy_pd_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool need_mem_protection;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) bool has_alt_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) bool has_mba_logs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) bool has_spare_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct q6v5 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct rproc *rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void __iomem *rmb_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct regmap *halt_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct regmap *conn_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 halt_q6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 halt_modem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 halt_nc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 conn_box;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct reset_control *mss_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct reset_control *pdc_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct qcom_q6v5 q6v5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct clk *active_clks[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct clk *reset_clks[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct clk *proxy_clks[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct device *active_pds[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct device *proxy_pds[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int active_clk_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int reset_clk_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int proxy_clk_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int active_pd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int proxy_pd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct reg_info active_regs[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct reg_info proxy_regs[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int active_reg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int proxy_reg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) bool dump_mba_loaded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) size_t current_dump_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) size_t total_dump_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) phys_addr_t mba_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) void *mba_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) size_t mba_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) size_t dp_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) phys_addr_t mpss_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) phys_addr_t mpss_reloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) size_t mpss_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct qcom_rproc_glink glink_subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct qcom_rproc_subdev smd_subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct qcom_rproc_ssr ssr_subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct qcom_sysmon *sysmon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) bool need_mem_protection;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) bool has_alt_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) bool has_mba_logs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) bool has_spare_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int mpss_perm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int mba_perm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) const char *hexagon_mdt_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MSS_MSM8916,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MSS_MSM8974,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MSS_MSM8996,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MSS_MSM8998,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MSS_SC7180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MSS_SDM845,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) const struct qcom_mss_reg_res *reg_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!reg_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (i = 0; reg_res[i].supply; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (IS_ERR(regs[i].reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) rc = PTR_ERR(regs[i].reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (rc != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev_err(dev, "Failed to get %s\n regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) reg_res[i].supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) regs[i].uV = reg_res[i].uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) regs[i].uA = reg_res[i].uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int q6v5_regulator_enable(struct q6v5 *qproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct reg_info *regs, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (regs[i].uV > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = regulator_set_voltage(regs[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) regs[i].uV, INT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_err(qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "Failed to request voltage for %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (regs[i].uA > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = regulator_set_load(regs[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) regs[i].uA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev_err(qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "Failed to set regulator mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ret = regulator_enable(regs[i].reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(qproc->dev, "Regulator enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) for (; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (regs[i].uV > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) regulator_set_voltage(regs[i].reg, 0, INT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (regs[i].uA > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) regulator_set_load(regs[i].reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) regulator_disable(regs[i].reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void q6v5_regulator_disable(struct q6v5 *qproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct reg_info *regs, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (regs[i].uV > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) regulator_set_voltage(regs[i].reg, 0, INT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (regs[i].uA > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) regulator_set_load(regs[i].reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) regulator_disable(regs[i].reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int q6v5_clk_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct clk **clks, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) rc = clk_prepare_enable(clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_err(dev, "Clock enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) for (i--; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) clk_disable_unprepare(clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void q6v5_clk_disable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct clk **clks, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) clk_disable_unprepare(clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) size_t pd_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) for (i = 0; i < pd_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ret = pm_runtime_get_sync(pds[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pm_runtime_put_noidle(pds[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dev_pm_genpd_set_performance_state(pds[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) goto unroll_pd_votes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unroll_pd_votes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) for (i--; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_pm_genpd_set_performance_state(pds[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pm_runtime_put(pds[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) size_t pd_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) for (i = 0; i < pd_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_pm_genpd_set_performance_state(pds[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pm_runtime_put(pds[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) bool local, bool remote, phys_addr_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct qcom_scm_vmperm next[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int perms = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!qproc->need_mem_protection)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (local == !!(*current_perm & BIT(QCOM_SCM_VMID_HLOS)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) remote == !!(*current_perm & BIT(QCOM_SCM_VMID_MSS_MSA)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (local) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) next[perms].vmid = QCOM_SCM_VMID_HLOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) next[perms].perm = QCOM_SCM_PERM_RWX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) perms++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (remote) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) next[perms].vmid = QCOM_SCM_VMID_MSS_MSA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) next[perms].perm = QCOM_SCM_PERM_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) perms++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) current_perm, next, perms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static void q6v5_debug_policy_load(struct q6v5 *qproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) const struct firmware *dp_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (request_firmware_direct(&dp_fw, "msadp", qproc->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (SZ_1M + dp_fw->size <= qproc->mba_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) memcpy(qproc->mba_region + SZ_1M, dp_fw->data, dp_fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) qproc->dp_size = dp_fw->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) release_firmware(dp_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct q6v5 *qproc = rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* MBA is restricted to a maximum size of 1M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev_err(qproc->dev, "MBA firmware load failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) memcpy(qproc->mba_region, fw->data, fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) q6v5_debug_policy_load(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int q6v5_reset_assert(struct q6v5 *qproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (qproc->has_alt_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) reset_control_assert(qproc->pdc_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = reset_control_reset(qproc->mss_restart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) reset_control_deassert(qproc->pdc_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) } else if (qproc->has_spare_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * When the AXI pipeline is being reset with the Q6 modem partly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * operational there is possibility of AXI valid signal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * glitch, leading to spurious transactions and Q6 hangs. A work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * around is employed by asserting the AXI_GATING_VALID_OVERRIDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * is withdrawn post MSS assert followed by a MSS deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * while holding the PDC reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) reset_control_assert(qproc->pdc_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) regmap_update_bits(qproc->conn_map, qproc->conn_box,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) AXI_GATING_VALID_OVERRIDE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) reset_control_assert(qproc->mss_restart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) reset_control_deassert(qproc->pdc_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) regmap_update_bits(qproc->conn_map, qproc->conn_box,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) AXI_GATING_VALID_OVERRIDE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = reset_control_deassert(qproc->mss_restart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = reset_control_assert(qproc->mss_restart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int q6v5_reset_deassert(struct q6v5 *qproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (qproc->has_alt_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) reset_control_assert(qproc->pdc_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ret = reset_control_reset(qproc->mss_restart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) reset_control_deassert(qproc->pdc_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) } else if (qproc->has_spare_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = reset_control_reset(qproc->mss_restart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = reset_control_deassert(qproc->mss_restart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) s32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) timeout = jiffies + msecs_to_jiffies(ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) s32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) timeout = jiffies + msecs_to_jiffies(ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (!status && val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) else if (status && val == status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static void q6v5_dump_mba_logs(struct q6v5 *qproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct rproc *rproc = qproc->rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!qproc->has_mba_logs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, qproc->mba_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) qproc->mba_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) data = vmalloc(MBA_LOG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) memcpy(data, qproc->mba_region, MBA_LOG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_coredumpv(&rproc->dev, data, MBA_LOG_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int q6v5proc_reset(struct q6v5 *qproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (qproc->version == MSS_SDM845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) val = readl(qproc->reg_base + QDSP6SS_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) val |= Q6SS_CBCR_CLKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) writel(val, qproc->reg_base + QDSP6SS_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) val, !(val & Q6SS_CBCR_CLKOFF), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) Q6SS_CBCR_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* De-assert QDSP6 stop core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Trigger boot FSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dev_err(qproc->dev, "Boot FSM failed to complete.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Reset the modem so that boot FSM is in reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) q6v5_reset_deassert(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) goto pbl_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) } else if (qproc->version == MSS_SC7180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) val = readl(qproc->reg_base + QDSP6SS_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) val |= Q6SS_CBCR_CLKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) writel(val, qproc->reg_base + QDSP6SS_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) val, !(val & Q6SS_CBCR_CLKOFF), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) Q6SS_CBCR_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* Turn on the XO clock needed for PLL setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) val |= Q6SS_CBCR_CLKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) val, !(val & Q6SS_CBCR_CLKOFF), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) Q6SS_CBCR_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_err(qproc->dev, "QDSP6SS XO clock timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Configure Q6 core CBCR to auto-enable after reset sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) val |= Q6SS_CBCR_CLKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* De-assert the Q6 stop core signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* Wait for 10 us for any staggering logic to settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* Trigger the boot FSM to start the Q6 out-of-reset sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Poll the MSS_STATUS for FSM completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dev_err(qproc->dev, "Boot FSM failed to complete.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Reset the modem so that boot FSM is in reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) q6v5_reset_deassert(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) goto pbl_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) } else if (qproc->version == MSS_MSM8996 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) qproc->version == MSS_MSM8998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) int mem_pwr_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* Override the ACC value if required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) writel(QDSP6SS_ACC_OVERRIDE_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) qproc->reg_base + QDSP6SS_STRAP_ACC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Assert resets, stop core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* BHS require xo cbcr to be enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) val |= Q6SS_CBCR_CLKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* Read CLKOFF bit to go low indicating CLK is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) val, !(val & Q6SS_CBCR_CLKOFF), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) Q6SS_CBCR_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dev_err(qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) "xo cbcr enabling timed out (rc:%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* Enable power block headswitch and wait for it to stabilize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) val |= QDSP6v56_BHS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Put LDO in bypass mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) val |= QDSP6v56_LDO_BYP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Deassert QDSP6 compiler memory clamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) val &= ~QDSP6v56_CLAMP_QMC_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* Deassert memory peripheral sleep and L2 memory standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Turn on L1, L2, ETB and JU memories 1 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (qproc->version == MSS_MSM8996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) i = 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* MSS_MSM8998 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) i = 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) val = readl(qproc->reg_base + mem_pwr_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) for (; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) val |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) writel(val, qproc->reg_base + mem_pwr_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * Read back value to ensure the write is done then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * wait for 1us for both memory peripheral and data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * array to turn on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) val |= readl(qproc->reg_base + mem_pwr_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* Remove word line clamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) val &= ~QDSP6v56_CLAMP_WL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* Assert resets, stop core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* Enable power block headswitch and wait for it to stabilize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) val |= QDSS_BHS_ON | QDSS_LDO_BYP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * Turn on memories. L2 banks should be done individually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * to minimize inrush current.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) val |= Q6SS_L2DATA_SLP_NRET_N_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) val |= Q6SS_L2DATA_SLP_NRET_N_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) val |= Q6SS_L2DATA_SLP_NRET_N_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Remove IO clamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) val &= ~Q6SS_CLAMP_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* Bring core out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) val &= ~Q6SS_CORE_ARES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* Turn on core clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) val |= Q6SS_CLK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* Start core execution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) val &= ~Q6SS_STOP_CORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) pbl_wait:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* Wait for PBL status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ret = q6v5_rmb_pbl_wait(qproc, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (ret == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dev_err(qproc->dev, "PBL boot timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) } else if (ret != RMB_PBL_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct regmap *halt_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Check if we're already idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (!ret && val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* Assert halt request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* Wait for halt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) regmap_read_poll_timeout(halt_map, offset + AXI_HALTACK_REG, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) val, 1000, HALT_ACK_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (ret || !val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev_err(qproc->dev, "port failed halt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* Clear halt request (port will remain halted until reset) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dma_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) void *metadata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int mdata_perm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int xferop_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) void *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) metadata = qcom_mdt_read_metadata(fw, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (IS_ERR(metadata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return PTR_ERR(metadata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (!ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) kfree(metadata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) dev_err(qproc->dev, "failed to allocate mdt buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) memcpy(ptr, metadata, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* Hypervisor mapping to access metadata by modem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) phys, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) dev_err(qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) "assigning Q6 access to metadata failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) goto free_dma_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (ret == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) dev_err(qproc->dev, "MPSS header authentication timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) else if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* Metadata authentication done, remove modem access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) phys, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (xferop_ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dev_warn(qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) "mdt buffer not reclaimed system may become unstable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) free_dma_attrs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) kfree(metadata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return ret < 0 ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (phdr->p_type != PT_LOAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (!phdr->p_memsz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static int q6v5_mba_load(struct q6v5 *qproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) int xfermemop_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) bool mba_load_err = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) qcom_q6v5_prepare(&qproc->q6v5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev_err(qproc->dev, "failed to enable active power domains\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) goto disable_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_err(qproc->dev, "failed to enable proxy power domains\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) goto disable_active_pds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) qproc->proxy_reg_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dev_err(qproc->dev, "failed to enable proxy supplies\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) goto disable_proxy_pds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) qproc->proxy_clk_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) dev_err(qproc->dev, "failed to enable proxy clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) goto disable_proxy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ret = q6v5_regulator_enable(qproc, qproc->active_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) qproc->active_reg_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dev_err(qproc->dev, "failed to enable supplies\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) goto disable_proxy_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) qproc->reset_clk_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dev_err(qproc->dev, "failed to enable reset clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) goto disable_vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ret = q6v5_reset_deassert(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dev_err(qproc->dev, "failed to deassert mss restart\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) goto disable_reset_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) qproc->active_clk_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dev_err(qproc->dev, "failed to enable clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) goto assert_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * the Q6 access to this region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) qproc->mpss_phys, qproc->mpss_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) dev_err(qproc->dev, "assigning Q6 access to mpss memory failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) goto disable_active_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* Assign MBA image access in DDR to q6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) qproc->mba_phys, qproc->mba_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) dev_err(qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) "assigning Q6 access to mba memory failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) goto disable_active_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (qproc->dp_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) writel(qproc->mba_phys + SZ_1M, qproc->rmb_base + RMB_PMI_CODE_START_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) writel(qproc->dp_size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ret = q6v5proc_reset(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) goto reclaim_mba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (ret == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) dev_err(qproc->dev, "MBA boot timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) goto halt_axi_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) } else if (ret != RMB_MBA_XPU_UNLOCKED &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) goto halt_axi_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) qproc->dump_mba_loaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) halt_axi_ports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) mba_load_err = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) reclaim_mba:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) false, qproc->mba_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) qproc->mba_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (xfermemop_ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) dev_err(qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) "Failed to reclaim mba buffer, system may become unstable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) } else if (mba_load_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) q6v5_dump_mba_logs(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) disable_active_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) q6v5_clk_disable(qproc->dev, qproc->active_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) qproc->active_clk_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) assert_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) q6v5_reset_assert(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) disable_reset_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) q6v5_clk_disable(qproc->dev, qproc->reset_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) qproc->reset_clk_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) disable_vdd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) q6v5_regulator_disable(qproc, qproc->active_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) qproc->active_reg_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) disable_proxy_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) qproc->proxy_clk_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) disable_proxy_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) q6v5_regulator_disable(qproc, qproc->proxy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) qproc->proxy_reg_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) disable_proxy_pds:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) disable_active_pds:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) disable_irqs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) qcom_q6v5_unprepare(&qproc->q6v5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static void q6v5_mba_reclaim(struct q6v5 *qproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) qproc->dump_mba_loaded = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) qproc->dp_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (qproc->version == MSS_MSM8996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * To avoid high MX current during LPASS/MSS restart.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) QDSP6v56_CLAMP_QMC_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) q6v5_reset_assert(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) q6v5_clk_disable(qproc->dev, qproc->reset_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) qproc->reset_clk_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) q6v5_clk_disable(qproc->dev, qproc->active_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) qproc->active_clk_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) q6v5_regulator_disable(qproc, qproc->active_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) qproc->active_reg_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* In case of failure or coredump scenario where reclaiming MBA memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * could not happen reclaim it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) qproc->mba_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) qproc->mba_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) WARN_ON(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ret = qcom_q6v5_unprepare(&qproc->q6v5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) q6v5_pds_disable(qproc, qproc->proxy_pds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) qproc->proxy_pd_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) qproc->proxy_clk_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) q6v5_regulator_disable(qproc, qproc->proxy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) qproc->proxy_reg_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static int q6v5_reload_mba(struct rproc *rproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct q6v5 *qproc = rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ret = request_firmware(&fw, rproc->firmware, qproc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) q6v5_load(rproc, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = q6v5_mba_load(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static int q6v5_mpss_load(struct q6v5 *qproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) const struct elf32_phdr *phdrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) const struct elf32_phdr *phdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) const struct firmware *seg_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct elf32_hdr *ehdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) phys_addr_t mpss_reloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) phys_addr_t boot_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) phys_addr_t min_addr = PHYS_ADDR_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) phys_addr_t max_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) u32 code_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) bool relocate = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) char *fw_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) size_t fw_name_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ssize_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) size_t size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) void *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) fw_name_len = strlen(qproc->hexagon_mdt_image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (fw_name_len <= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (!fw_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ret = request_firmware(&fw, fw_name, qproc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) dev_err(qproc->dev, "unable to load %s\n", fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* Initialize the RMB validator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ret = q6v5_mpss_init_image(qproc, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) goto release_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ehdr = (struct elf32_hdr *)fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) phdrs = (struct elf32_phdr *)(ehdr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) for (i = 0; i < ehdr->e_phnum; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) phdr = &phdrs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (!q6v5_phdr_valid(phdr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) relocate = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (phdr->p_paddr < min_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) min_addr = phdr->p_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (phdr->p_paddr + phdr->p_memsz > max_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * In case of a modem subsystem restart on secure devices, the modem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * memory can be reclaimed only after MBA is loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) qproc->mpss_phys, qproc->mpss_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Share ownership between Linux and MSS, during segment loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) qproc->mpss_phys, qproc->mpss_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) dev_err(qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) "assigning Q6 access to mpss memory failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) goto release_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) qproc->mpss_reloc = mpss_reloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* Load firmware segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) for (i = 0; i < ehdr->e_phnum; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) phdr = &phdrs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (!q6v5_phdr_valid(phdr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) offset = phdr->p_paddr - mpss_reloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) dev_err(qproc->dev, "segment outside memory range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) goto release_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (phdr->p_filesz > phdr->p_memsz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) dev_err(qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) "refusing to load segment %d with p_filesz > p_memsz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) goto release_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ptr = memremap(qproc->mpss_phys + offset, phdr->p_memsz, MEMREMAP_WC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (!ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) dev_err(qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) "unable to map memory region: %pa+%zx-%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) &qproc->mpss_phys, offset, phdr->p_memsz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) goto release_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (phdr->p_filesz && phdr->p_offset < fw->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /* Firmware is large enough to be non-split */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (phdr->p_offset + phdr->p_filesz > fw->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) dev_err(qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) "failed to load segment %d from truncated file %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) i, fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) memunmap(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) goto release_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) } else if (phdr->p_filesz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /* Replace "xxx.xxx" with "xxx.bxx" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) sprintf(fw_name + fw_name_len - 3, "b%02d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) ret = request_firmware_into_buf(&seg_fw, fw_name, qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ptr, phdr->p_filesz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) dev_err(qproc->dev, "failed to load %s\n", fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) memunmap(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) goto release_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (seg_fw->size != phdr->p_filesz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) dev_err(qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) "failed to load segment %d from truncated file %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) i, fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) release_firmware(seg_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) memunmap(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) goto release_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) release_firmware(seg_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (phdr->p_memsz > phdr->p_filesz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) memset(ptr + phdr->p_filesz, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) phdr->p_memsz - phdr->p_filesz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) memunmap(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) size += phdr->p_memsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) code_length = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (!code_length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) boot_addr = relocate ? qproc->mpss_phys : min_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) ret = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) dev_err(qproc->dev, "MPSS authentication failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) goto release_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /* Transfer ownership of modem ddr region to q6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) qproc->mpss_phys, qproc->mpss_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) dev_err(qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) "assigning Q6 access to mpss memory failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) goto release_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (ret == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) dev_err(qproc->dev, "MPSS authentication timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) else if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) qcom_pil_info_store("modem", qproc->mpss_phys, qproc->mpss_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) release_firmware:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) kfree(fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return ret < 0 ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static void qcom_q6v5_dump_segment(struct rproc *rproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct rproc_dump_segment *segment,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) void *dest, size_t cp_offset, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) struct q6v5 *qproc = rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) int offset = segment->da - qproc->mpss_reloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) void *ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* Unlock mba before copying segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (!qproc->dump_mba_loaded) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ret = q6v5_reload_mba(rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /* Reset ownership back to Linux to copy segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) true, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) qproc->mpss_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) qproc->mpss_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) ptr = memremap(qproc->mpss_phys + offset + cp_offset, size, MEMREMAP_WC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) memcpy(dest, ptr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) memunmap(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) memset(dest, 0xff, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) qproc->current_dump_size += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* Reclaim mba after copying segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (qproc->current_dump_size == qproc->total_dump_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (qproc->dump_mba_loaded) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /* Try to reset ownership back to Q6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) false, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) qproc->mpss_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) qproc->mpss_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) q6v5_mba_reclaim(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static int q6v5_start(struct rproc *rproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) int xfermemop_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) ret = q6v5_mba_load(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) dev_info(qproc->dev, "MBA booted with%s debug policy, loading mpss\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) qproc->dp_size ? "" : "out");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ret = q6v5_mpss_load(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) goto reclaim_mpss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (ret == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) dev_err(qproc->dev, "start timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) goto reclaim_mpss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) false, qproc->mba_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) qproc->mba_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (xfermemop_ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) dev_err(qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) "Failed to reclaim mba buffer system may become unstable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) /* Reset Dump Segment Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) qproc->current_dump_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) reclaim_mpss:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) q6v5_mba_reclaim(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) q6v5_dump_mba_logs(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static int q6v5_stop(struct rproc *rproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) ret = qcom_q6v5_request_stop(&qproc->q6v5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if (ret == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) dev_err(qproc->dev, "timed out on wait\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) q6v5_mba_reclaim(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) const struct firmware *mba_fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) const struct elf32_phdr *phdrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) const struct elf32_phdr *phdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) const struct elf32_hdr *ehdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) struct q6v5 *qproc = rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) unsigned long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) dev_err(qproc->dev, "unable to load %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) qproc->hexagon_mdt_image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) ehdr = (struct elf32_hdr *)fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) phdrs = (struct elf32_phdr *)(ehdr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) qproc->total_dump_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) for (i = 0; i < ehdr->e_phnum; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) phdr = &phdrs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (!q6v5_phdr_valid(phdr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) phdr->p_memsz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) qcom_q6v5_dump_segment,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) qproc->total_dump_size += phdr->p_memsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static const struct rproc_ops q6v5_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .start = q6v5_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .stop = q6v5_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .parse_fw = qcom_q6v5_register_dump_segments,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .load = q6v5_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) qproc->proxy_clk_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) q6v5_regulator_disable(qproc, qproc->proxy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) qproc->proxy_reg_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) struct of_phandle_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (IS_ERR(qproc->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) return PTR_ERR(qproc->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (IS_ERR(qproc->rmb_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return PTR_ERR(qproc->rmb_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) "qcom,halt-regs", 3, 0, &args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) qproc->halt_map = syscon_node_to_regmap(args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) of_node_put(args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (IS_ERR(qproc->halt_map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return PTR_ERR(qproc->halt_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) qproc->halt_q6 = args.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) qproc->halt_modem = args.args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) qproc->halt_nc = args.args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (qproc->has_spare_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) "qcom,spare-regs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) 1, 0, &args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) dev_err(&pdev->dev, "failed to parse spare-regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) qproc->conn_map = syscon_node_to_regmap(args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) of_node_put(args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (IS_ERR(qproc->conn_map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) return PTR_ERR(qproc->conn_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) qproc->conn_box = args.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) static int q6v5_init_clocks(struct device *dev, struct clk **clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) char **clk_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) if (!clk_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) for (i = 0; clk_names[i]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) clks[i] = devm_clk_get(dev, clk_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if (IS_ERR(clks[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) int rc = PTR_ERR(clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (rc != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) dev_err(dev, "Failed to get %s clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) clk_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static int q6v5_pds_attach(struct device *dev, struct device **devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) char **pd_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) size_t num_pds = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (!pd_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) while (pd_names[num_pds])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) num_pds++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) for (i = 0; i < num_pds; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (IS_ERR_OR_NULL(devs[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) ret = PTR_ERR(devs[i]) ? : -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) goto unroll_attach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) return num_pds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) unroll_attach:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) for (i--; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) dev_pm_domain_detach(devs[i], false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) size_t pd_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) for (i = 0; i < pd_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) dev_pm_domain_detach(pds[i], false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) static int q6v5_init_reset(struct q6v5 *qproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) "mss_restart");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (IS_ERR(qproc->mss_restart)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) dev_err(qproc->dev, "failed to acquire mss restart\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) return PTR_ERR(qproc->mss_restart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) if (qproc->has_alt_reset || qproc->has_spare_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) "pdc_reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if (IS_ERR(qproc->pdc_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) dev_err(qproc->dev, "failed to acquire pdc reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) return PTR_ERR(qproc->pdc_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static int q6v5_alloc_memory_region(struct q6v5 *qproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) struct resource r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) * In the absence of mba/mpss sub-child, extract the mba and mpss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) * reserved memory regions from device's memory-region property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) child = of_get_child_by_name(qproc->dev->of_node, "mba");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (!child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) node = of_parse_phandle(qproc->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) "memory-region", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) node = of_parse_phandle(child, "memory-region", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) ret = of_address_to_resource(node, 0, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) dev_err(qproc->dev, "unable to resolve mba region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) qproc->mba_phys = r.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) qproc->mba_size = resource_size(&r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (!qproc->mba_region) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) &r.start, qproc->mba_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (!child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) node = of_parse_phandle(qproc->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) "memory-region", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) child = of_get_child_by_name(qproc->dev->of_node, "mpss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) node = of_parse_phandle(child, "memory-region", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) ret = of_address_to_resource(node, 0, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) dev_err(qproc->dev, "unable to resolve mpss region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) qproc->mpss_phys = qproc->mpss_reloc = r.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) qproc->mpss_size = resource_size(&r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static int q6v5_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) const struct rproc_hexagon_res *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) struct q6v5 *qproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) struct rproc *rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) const char *mba_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) desc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (desc->need_mem_protection && !qcom_scm_is_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) mba_image = desc->hexagon_mba_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) 0, &mba_image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (ret < 0 && ret != -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) mba_image, sizeof(*qproc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (!rproc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) dev_err(&pdev->dev, "failed to allocate rproc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) rproc->auto_boot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) qproc = (struct q6v5 *)rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) qproc->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) qproc->rproc = rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) qproc->hexagon_mdt_image = "modem.mdt";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) 1, &qproc->hexagon_mdt_image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (ret < 0 && ret != -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) platform_set_drvdata(pdev, qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) qproc->has_spare_reg = desc->has_spare_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) ret = q6v5_init_mem(qproc, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) ret = q6v5_alloc_memory_region(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) desc->proxy_clk_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) qproc->proxy_clk_count = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) desc->reset_clk_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) dev_err(&pdev->dev, "Failed to get reset clocks.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) qproc->reset_clk_count = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) desc->active_clk_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) dev_err(&pdev->dev, "Failed to get active clocks.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) qproc->active_clk_count = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) desc->proxy_supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) qproc->proxy_reg_count = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) desc->active_supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) dev_err(&pdev->dev, "Failed to get active regulators.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) qproc->active_reg_count = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) desc->active_pd_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) dev_err(&pdev->dev, "Failed to attach active power domains\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) qproc->active_pd_count = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) desc->proxy_pd_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) dev_err(&pdev->dev, "Failed to init power domains\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) goto detach_active_pds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) qproc->proxy_pd_count = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) qproc->has_alt_reset = desc->has_alt_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) ret = q6v5_init_reset(qproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) goto detach_proxy_pds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) qproc->version = desc->version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) qproc->need_mem_protection = desc->need_mem_protection;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) qproc->has_mba_logs = desc->has_mba_logs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) qcom_msa_handover);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) goto detach_proxy_pds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) qcom_add_glink_subdev(rproc, &qproc->glink_subdev, "mpss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) if (IS_ERR(qproc->sysmon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) ret = PTR_ERR(qproc->sysmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) goto remove_subdevs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) ret = rproc_add(rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) goto remove_sysmon_subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) remove_sysmon_subdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) qcom_remove_sysmon_subdev(qproc->sysmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) remove_subdevs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) detach_proxy_pds:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) detach_active_pds:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) free_rproc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) rproc_free(rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) static int q6v5_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) struct q6v5 *qproc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) struct rproc *rproc = qproc->rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) rproc_del(rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) qcom_remove_sysmon_subdev(qproc->sysmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) rproc_free(rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) static const struct rproc_hexagon_res sc7180_mss = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .hexagon_mba_image = "mba.mbn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .proxy_clk_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .reset_clk_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) "iface",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) "bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) "snoc_axi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .active_clk_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) "mnoc_axi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) "nav",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .active_pd_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) "load_state",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .proxy_pd_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) "cx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) "mx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) "mss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .need_mem_protection = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .has_alt_reset = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .has_mba_logs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .has_spare_reg = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .version = MSS_SC7180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) static const struct rproc_hexagon_res sdm845_mss = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .hexagon_mba_image = "mba.mbn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .proxy_clk_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) "prng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .reset_clk_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) "iface",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) "snoc_axi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .active_clk_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) "bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) "mem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) "gpll0_mss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) "mnoc_axi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .active_pd_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) "load_state",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .proxy_pd_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) "cx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) "mx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) "mss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .need_mem_protection = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .has_alt_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .has_mba_logs = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .has_spare_reg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .version = MSS_SDM845,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) static const struct rproc_hexagon_res msm8998_mss = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .hexagon_mba_image = "mba.mbn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .proxy_clk_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) "qdss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) "mem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .active_clk_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) "iface",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) "bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) "gpll0_mss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) "mnoc_axi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) "snoc_axi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .proxy_pd_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) "cx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) "mx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .need_mem_protection = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .has_alt_reset = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .has_mba_logs = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .has_spare_reg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .version = MSS_MSM8998,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) static const struct rproc_hexagon_res msm8996_mss = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .hexagon_mba_image = "mba.mbn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .proxy_supply = (struct qcom_mss_reg_res[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .supply = "pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .uA = 100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .proxy_clk_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) "pnoc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) "qdss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .active_clk_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) "iface",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) "bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) "mem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) "gpll0_mss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) "snoc_axi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) "mnoc_axi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .need_mem_protection = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .has_alt_reset = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .has_mba_logs = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .has_spare_reg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .version = MSS_MSM8996,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) static const struct rproc_hexagon_res msm8916_mss = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .hexagon_mba_image = "mba.mbn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .proxy_supply = (struct qcom_mss_reg_res[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .supply = "mx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .uV = 1050000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .supply = "cx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .uA = 100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .supply = "pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .uA = 100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .proxy_clk_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .active_clk_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) "iface",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) "bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) "mem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .need_mem_protection = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .has_alt_reset = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .has_mba_logs = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .has_spare_reg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .version = MSS_MSM8916,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) static const struct rproc_hexagon_res msm8974_mss = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .hexagon_mba_image = "mba.b00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .proxy_supply = (struct qcom_mss_reg_res[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .supply = "mx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .uV = 1050000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .supply = "cx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .uA = 100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .supply = "pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .uA = 100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .active_supply = (struct qcom_mss_reg_res[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .supply = "mss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .uV = 1050000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .uA = 100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .proxy_clk_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .active_clk_names = (char*[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) "iface",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) "bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) "mem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .need_mem_protection = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .has_alt_reset = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .has_mba_logs = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .has_spare_reg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .version = MSS_MSM8974,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static const struct of_device_id q6v5_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) MODULE_DEVICE_TABLE(of, q6v5_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) static struct platform_driver q6v5_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .probe = q6v5_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .remove = q6v5_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .name = "qcom-q6v5-mss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .of_match_table = q6v5_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) module_platform_driver(q6v5_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags