^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __RPROC_MTK_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __RPROC_MTK_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/remoteproc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/remoteproc/mtk_scp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MT8183_SW_RSTN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MT8183_SW_RSTN_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MT8183_SCP_TO_HOST 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MT8183_SCP_IPC_INT_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MT8183_SCP_WDT_INT_BIT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MT8183_HOST_TO_SCP 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MT8183_HOST_IPC_INT_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MT8183_WDT_CFG 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MT8183_SCP_CLK_SW_SEL 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MT8183_SCP_CLK_DIV_SEL 0x4024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MT8183_SCP_SRAM_PDN 0x402C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MT8183_SCP_L1_SRAM_PD 0x4080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MT8183_SCP_TCM_TAIL_SRAM_PD 0x4094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MT8183_SCP_CACHE_SEL(x) (0x14000 + (x) * 0x3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MT8183_SCP_CACHE_CON MT8183_SCP_CACHE_SEL(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MT8183_SCP_DCACHE_CON MT8183_SCP_CACHE_SEL(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MT8183_SCP_CACHESIZE_8KB BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MT8183_SCP_CACHE_CON_WAYEN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MT8192_L2TCM_SRAM_PD_0 0x10C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MT8192_L2TCM_SRAM_PD_1 0x10C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MT8192_L2TCM_SRAM_PD_2 0x10C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MT8192_L1TCM_SRAM_PDN 0x102C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MT8192_CPU0_SRAM_PD 0x1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MT8192_SCP2APMCU_IPC_SET 0x4080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MT8192_SCP2APMCU_IPC_CLR 0x4084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MT8192_SCP_IPC_INT_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MT8192_SCP2SPM_IPC_CLR 0x4094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MT8192_GIPC_IN_SET 0x4098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MT8192_HOST_IPC_INT_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MT8192_CORE0_SW_RSTN_CLR 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MT8192_CORE0_SW_RSTN_SET 0x10004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MT8192_CORE0_WDT_IRQ 0x10030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MT8192_CORE0_WDT_CFG 0x10034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SCP_FW_VER_LEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SCP_SHARE_BUFFER_SIZE 288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct scp_run {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 signaled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) s8 fw_ver[SCP_FW_VER_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 dec_capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 enc_capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) wait_queue_head_t wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct scp_ipi_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* For protecting handler. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) scp_ipi_handler_t handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct mtk_scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct mtk_scp_of_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int (*scp_before_load)(struct mtk_scp *scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void (*scp_irq_handler)(struct mtk_scp *scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void (*scp_reset_assert)(struct mtk_scp *scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void (*scp_reset_deassert)(struct mtk_scp *scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void (*scp_stop)(struct mtk_scp *scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 host_to_scp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 host_to_scp_int_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct mtk_scp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct rproc *rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) void __iomem *sram_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) size_t sram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const struct mtk_scp_of_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct mtk_share_obj __iomem *recv_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct mtk_share_obj __iomem *send_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct scp_run run;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* To prevent multiple ipi_send run concurrently. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct mutex send_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct scp_ipi_desc ipi_desc[SCP_IPI_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) bool ipi_id_ack[SCP_IPI_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) wait_queue_head_t ack_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void __iomem *cpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) size_t dram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct rproc_subdev *rpmsg_subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * struct mtk_share_obj - SRAM buffer shared with AP and SCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @id: IPI id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @len: share buffer length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @share_buf: share buffer data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct mtk_share_obj {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 share_buf[SCP_SHARE_BUFFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void scp_memcpy_aligned(void __iomem *dst, const void *src, unsigned int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void scp_ipi_lock(struct mtk_scp *scp, u32 id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void scp_ipi_unlock(struct mtk_scp *scp, u32 id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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