Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Ingenic JZ47xx remoteproc driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2019, Paul Cercueil <paul@crapouillou.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/remoteproc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "remoteproc_internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define REG_AUX_CTRL		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define REG_AUX_MSG_ACK		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define REG_AUX_MSG		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define REG_CORE_MSG_ACK	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define REG_CORE_MSG		0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AUX_CTRL_SLEEP		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AUX_CTRL_MSG_IRQ_EN	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AUX_CTRL_NMI_RESETS	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AUX_CTRL_NMI		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AUX_CTRL_SW_RESET	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) struct vpu_mem_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	unsigned int da;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct vpu_mem_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	const struct vpu_mem_map *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	unsigned long len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static const struct vpu_mem_map vpu_mem_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	{ "tcsm0", 0x132b0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	{ "tcsm1", 0xf4000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	{ "sram",  0x132f0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * struct vpu - Ingenic VPU remoteproc private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * @irq: interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * @clks: pointers to the VPU and AUX clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * @aux_base: raw pointer to the AUX interface registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * @mem_info: array of struct vpu_mem_info, which contain the mapping info of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  *            each of the external memories
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * @dev: private pointer to the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) struct vpu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct clk_bulk_data clks[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	void __iomem *aux_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct vpu_mem_info mem_info[ARRAY_SIZE(vpu_mem_map)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static int ingenic_rproc_prepare(struct rproc *rproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct vpu *vpu = rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	/* The clocks must be enabled for the firmware to be loaded in TCSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	ret = clk_bulk_prepare_enable(ARRAY_SIZE(vpu->clks), vpu->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		dev_err(vpu->dev, "Unable to start clocks: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int ingenic_rproc_unprepare(struct rproc *rproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct vpu *vpu = rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	clk_bulk_disable_unprepare(ARRAY_SIZE(vpu->clks), vpu->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int ingenic_rproc_start(struct rproc *rproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct vpu *vpu = rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	enable_irq(vpu->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/* Reset the AUX and enable message IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	ctrl = AUX_CTRL_NMI_RESETS | AUX_CTRL_NMI | AUX_CTRL_MSG_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	writel(ctrl, vpu->aux_base + REG_AUX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int ingenic_rproc_stop(struct rproc *rproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct vpu *vpu = rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	disable_irq(vpu->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/* Keep AUX in reset mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	writel(AUX_CTRL_SW_RESET, vpu->aux_base + REG_AUX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void ingenic_rproc_kick(struct rproc *rproc, int vqid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct vpu *vpu = rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	writel(vqid, vpu->aux_base + REG_CORE_MSG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void *ingenic_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct vpu *vpu = rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	void __iomem *va = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	for (i = 0; i < ARRAY_SIZE(vpu_mem_map); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		const struct vpu_mem_info *info = &vpu->mem_info[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		const struct vpu_mem_map *map = info->map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		if (da >= map->da && (da + len) < (map->da + info->len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			va = info->base + (da - map->da);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return (__force void *)va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct rproc_ops ingenic_rproc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.prepare = ingenic_rproc_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.unprepare = ingenic_rproc_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.start = ingenic_rproc_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.stop = ingenic_rproc_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.kick = ingenic_rproc_kick,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.da_to_va = ingenic_rproc_da_to_va,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static irqreturn_t vpu_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct rproc *rproc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct vpu *vpu = rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	u32 vring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	vring = readl(vpu->aux_base + REG_AUX_MSG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	/* Ack the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	writel(0, vpu->aux_base + REG_AUX_MSG_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return rproc_vq_interrupt(rproc, vring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int ingenic_rproc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct rproc *rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct vpu *vpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	rproc = devm_rproc_alloc(dev, "ingenic-vpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 				 &ingenic_rproc_ops, NULL, sizeof(*vpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (!rproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	vpu = rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	vpu->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	platform_set_drvdata(pdev, vpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aux");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	vpu->aux_base = devm_ioremap_resource(dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (IS_ERR(vpu->aux_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		dev_err(dev, "Failed to ioremap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return PTR_ERR(vpu->aux_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	for (i = 0; i < ARRAY_SIZE(vpu_mem_map); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		mem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 						   vpu_mem_map[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		vpu->mem_info[i].base = devm_ioremap_resource(dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		if (IS_ERR(vpu->mem_info[i].base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			ret = PTR_ERR(vpu->mem_info[i].base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			dev_err(dev, "Failed to ioremap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		vpu->mem_info[i].len = resource_size(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		vpu->mem_info[i].map = &vpu_mem_map[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	vpu->clks[0].id = "vpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	vpu->clks[1].id = "aux";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	ret = devm_clk_bulk_get(dev, ARRAY_SIZE(vpu->clks), vpu->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		dev_err(dev, "Failed to get clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	vpu->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (vpu->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return vpu->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	ret = devm_request_irq(dev, vpu->irq, vpu_interrupt, 0, "VPU", rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		dev_err(dev, "Failed to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	disable_irq(vpu->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	ret = devm_rproc_add(dev, rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		dev_err(dev, "Failed to register remote processor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct of_device_id ingenic_rproc_of_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	{ .compatible = "ingenic,jz4770-vpu-rproc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MODULE_DEVICE_TABLE(of, ingenic_rproc_of_matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static struct platform_driver ingenic_rproc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.probe = ingenic_rproc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		.name = "ingenic-vpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		.of_match_table = ingenic_rproc_of_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) module_platform_driver(ingenic_rproc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MODULE_DESCRIPTION("Ingenic JZ47xx Remote Processor control driver");