^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Remote processor machine-specific module for DA8XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_reserved_mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/remoteproc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "remoteproc_internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static char *da8xx_fw_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) module_param(da8xx_fw_name, charp, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MODULE_PARM_DESC(da8xx_fw_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) "Name of DSP firmware file in /lib/firmware (if not specified defaults to 'rproc-dsp-fw')");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * OMAP-L138 Technical References:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * http://www.ti.com/product/omap-l138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SYSCFG_CHIPSIG0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SYSCFG_CHIPSIG1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SYSCFG_CHIPSIG2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SYSCFG_CHIPSIG3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SYSCFG_CHIPSIG4 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DA8XX_RPROC_LOCAL_ADDRESS_MASK (SZ_16M - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * struct da8xx_rproc_mem - internal memory structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @cpu_addr: MPU virtual address of the memory region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @bus_addr: Bus address used to access the memory region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @dev_addr: Device address of the memory region from DSP view
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @size: Size of the memory region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct da8xx_rproc_mem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void __iomem *cpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) phys_addr_t bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * struct da8xx_rproc - da8xx remote processor instance state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @rproc: rproc handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @mem: internal memory regions data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @num_mems: number of internal memory regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @dsp_clk: placeholder for platform's DSP clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @ack_fxn: chip-specific ack function for ack'ing irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @irq_data: ack_fxn function parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @chipsig: virt ptr to DSP interrupt registers (CHIPSIG & CHIPSIG_CLR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @bootreg: virt ptr to DSP boot address register (HOST1CFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @irq: irq # used by this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct da8xx_rproc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct rproc *rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct da8xx_rproc_mem *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int num_mems;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct clk *dsp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct reset_control *dsp_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void (*ack_fxn)(struct irq_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct irq_data *irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) void __iomem *chipsig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void __iomem *bootreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * handle_event() - inbound virtqueue message workqueue function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * This function is registered as a kernel thread and is scheduled by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * kernel handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static irqreturn_t handle_event(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct rproc *rproc = (struct rproc *)p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Process incoming buffers on all our vrings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) rproc_vq_interrupt(rproc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) rproc_vq_interrupt(rproc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * da8xx_rproc_callback() - inbound virtqueue message handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * This handler is invoked directly by the kernel whenever the remote
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * core (DSP) has modified the state of a virtqueue. There is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * "payload" message indicating the virtqueue index as is the case with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * mailbox-based implementations on OMAP4. As such, this handler "polls"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * each known virtqueue index for every invocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static irqreturn_t da8xx_rproc_callback(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct rproc *rproc = (struct rproc *)p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct da8xx_rproc *drproc = (struct da8xx_rproc *)rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 chipsig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) chipsig = readl(drproc->chipsig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (chipsig & SYSCFG_CHIPSIG0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Clear interrupt level source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) writel(SYSCFG_CHIPSIG0, drproc->chipsig + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * ACK intr to AINTC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * It has already been ack'ed by the kernel before calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * this function, but since the ARM<->DSP interrupts in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * CHIPSIG register are "level" instead of "pulse" variety,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * we need to ack it after taking down the level else we'll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * be called again immediately after returning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) drproc->ack_fxn(drproc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int da8xx_rproc_start(struct rproc *rproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct device *dev = rproc->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct da8xx_rproc *drproc = (struct da8xx_rproc *)rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct clk *dsp_clk = drproc->dsp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct reset_control *dsp_reset = drproc->dsp_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* hw requires the start (boot) address be on 1KB boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (rproc->bootaddr & 0x3ff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev_err(dev, "invalid boot address: must be aligned to 1KB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writel(rproc->bootaddr, drproc->bootreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = clk_prepare_enable(dsp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev_err(dev, "clk_prepare_enable() failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = reset_control_deassert(dsp_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dev_err(dev, "reset_control_deassert() failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) clk_disable_unprepare(dsp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int da8xx_rproc_stop(struct rproc *rproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct da8xx_rproc *drproc = rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct device *dev = rproc->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = reset_control_assert(drproc->dsp_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev_err(dev, "reset_control_assert() failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) clk_disable_unprepare(drproc->dsp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* kick a virtqueue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void da8xx_rproc_kick(struct rproc *rproc, int vqid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct da8xx_rproc *drproc = (struct da8xx_rproc *)rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Interrupt remote proc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writel(SYSCFG_CHIPSIG2, drproc->chipsig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct rproc_ops da8xx_rproc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .start = da8xx_rproc_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .stop = da8xx_rproc_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .kick = da8xx_rproc_kick,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int da8xx_rproc_get_internal_memories(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct da8xx_rproc *drproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const char * const mem_names[] = {"l2sram", "l1pram", "l1dram"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int num_mems = ARRAY_SIZE(mem_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) drproc->mem = devm_kcalloc(dev, num_mems, sizeof(*drproc->mem),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!drproc->mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) for (i = 0; i < num_mems; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mem_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) drproc->mem[i].cpu_addr = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (IS_ERR(drproc->mem[i].cpu_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dev_err(dev, "failed to parse and map %s memory\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mem_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return PTR_ERR(drproc->mem[i].cpu_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) drproc->mem[i].bus_addr = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) drproc->mem[i].dev_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) res->start & DA8XX_RPROC_LOCAL_ADDRESS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) drproc->mem[i].size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_dbg(dev, "memory %8s: bus addr %pa size 0x%zx va %p da 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mem_names[i], &drproc->mem[i].bus_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) drproc->mem[i].size, drproc->mem[i].cpu_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) drproc->mem[i].dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) drproc->num_mems = num_mems;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int da8xx_rproc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct da8xx_rproc *drproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct rproc *rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct irq_data *irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct resource *bootreg_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct resource *chipsig_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct clk *dsp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct reset_control *dsp_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) void __iomem *chipsig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) void __iomem *bootreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) irq_data = irq_get_irq_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!irq_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_err(dev, "irq_get_irq_data(%d): NULL\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) bootreg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "host1cfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) bootreg = devm_ioremap_resource(dev, bootreg_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (IS_ERR(bootreg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return PTR_ERR(bootreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) chipsig_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "chipsig");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) chipsig = devm_ioremap_resource(dev, chipsig_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (IS_ERR(chipsig))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return PTR_ERR(chipsig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dsp_clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (IS_ERR(dsp_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_err(dev, "clk_get error: %ld\n", PTR_ERR(dsp_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return PTR_ERR(dsp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dsp_reset = devm_reset_control_get_exclusive(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (IS_ERR(dsp_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (PTR_ERR(dsp_reset) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_err(dev, "unable to get reset control: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PTR_ERR(dsp_reset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return PTR_ERR(dsp_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = of_reserved_mem_device_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_err(dev, "device does not have specific CMA pool: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) rproc = rproc_alloc(dev, "dsp", &da8xx_rproc_ops, da8xx_fw_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) sizeof(*drproc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (!rproc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) goto free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* error recovery is not supported at present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) rproc->recovery_disabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) drproc = rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) drproc->rproc = rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) drproc->dsp_clk = dsp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) drproc->dsp_reset = dsp_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) rproc->has_iommu = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = da8xx_rproc_get_internal_memories(pdev, drproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) platform_set_drvdata(pdev, rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* everything the ISR needs is now setup, so hook it up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = devm_request_threaded_irq(dev, irq, da8xx_rproc_callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) handle_event, 0, "da8xx-remoteproc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dev_err(dev, "devm_request_threaded_irq error: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * rproc_add() can end up enabling the DSP's clk with the DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * *not* in reset, but da8xx_rproc_start() needs the DSP to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * held in reset at the time it is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = reset_control_assert(dsp_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) drproc->chipsig = chipsig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) drproc->bootreg = bootreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) drproc->ack_fxn = irq_data->chip->irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) drproc->irq_data = irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) drproc->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret = rproc_add(rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev_err(dev, "rproc_add failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) goto free_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) free_rproc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) rproc_free(rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) free_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) of_reserved_mem_device_release(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int da8xx_rproc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct rproc *rproc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct da8xx_rproc *drproc = (struct da8xx_rproc *)rproc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * The devm subsystem might end up releasing things before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * freeing the irq, thus allowing an interrupt to sneak in while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * the device is being removed. This should prevent that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) disable_irq(drproc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) rproc_del(rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) rproc_free(rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) of_reserved_mem_device_release(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct of_device_id davinci_rproc_of_match[] __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { .compatible = "ti,da850-dsp", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MODULE_DEVICE_TABLE(of, davinci_rproc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct platform_driver da8xx_rproc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .probe = da8xx_rproc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .remove = da8xx_rproc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .name = "davinci-rproc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .of_match_table = of_match_ptr(davinci_rproc_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) module_platform_driver(da8xx_rproc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MODULE_DESCRIPTION("DA8XX Remote Processor control driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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