Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Regulator driver for xz3216 DCDC chip for rk32xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2010, 2011 ROCKCHIP, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Based on xz3216.c that is work by zhangqing<zhangqing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DBG(x...)	pr_info(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DBG(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DBG_ERR(x...)	pr_err(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define XZ3216_NUM_REGULATORS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define XZ3216_BUCK1_SET_VOL_BASE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define XZ3216_BUCK1_SLP_VOL_BASE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define XZ3216_CONTR_REG1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define XZ3216_ID1_REG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define BUCK_VOL_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define VOL_MIN_IDX 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define VOL_MAX_IDX 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* VSEL bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define VSEL_BUCK_EN	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define VSEL_MODE	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define VSEL_NSEL_MASK	0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* Control bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CTL_OUTPUT_DISCHG	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CTL_SLEW_MASK		(0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CTL_SLEW_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CTL_RESET		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) struct xz3216 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct i2c_client *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	int num_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct regulator_init_data *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	/* Voltage setting register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	unsigned int vol_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	unsigned int sleep_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/* Voltage range and step(linear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	unsigned int vsel_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	unsigned int vsel_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	unsigned int sleep_vol_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) struct xz3216_regulator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct device		*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct regulator_desc	*desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct regulator_dev	*rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) struct xz3216_board {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct regulator_init_data *xz3216_init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct device_node *of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static unsigned int xz3216_dcdc_get_mode(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct xz3216 *xz3216 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	ret = regmap_read(xz3216->regmap, xz3216->vol_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (val & VSEL_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return REGULATOR_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int xz3216_dcdc_set_mode(struct regulator_dev *dev, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct xz3216 *xz3216 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	case REGULATOR_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return regmap_update_bits(xz3216->regmap, xz3216->vol_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 					  VSEL_MODE, VSEL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		return regmap_update_bits(xz3216->regmap, xz3216->vol_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 					  VSEL_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		DBG("error:dcdc_xz3216 only auto and pwm mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int xz3216_dcdc_suspend_enable(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct xz3216 *xz3216 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return regmap_update_bits(xz3216->regmap, XZ3216_BUCK1_SLP_VOL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				  VSEL_BUCK_EN, VSEL_BUCK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int xz3216_dcdc_suspend_disable(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct xz3216 *xz3216 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	return regmap_update_bits(xz3216->regmap, XZ3216_BUCK1_SLP_VOL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 				  VSEL_BUCK_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int xz3216_dcdc_set_sleep_voltage(struct regulator_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 					 int uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct xz3216 *xz3216 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (xz3216->sleep_vol_cache == uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	ret = regulator_map_voltage_linear(dev, uV, uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ret = regmap_update_bits(xz3216->regmap, XZ3216_BUCK1_SLP_VOL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 					VSEL_NSEL_MASK, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	xz3216->sleep_vol_cache = uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int xz3216_dcdc_set_suspend_mode(struct regulator_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 					 unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct xz3216 *xz3216 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	case REGULATOR_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		return regmap_update_bits(xz3216->regmap, xz3216->vol_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 					  VSEL_MODE, VSEL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		return regmap_update_bits(xz3216->regmap, xz3216->vol_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 					  VSEL_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		DBG_ERR("error:dcdc_xz3216 only auto and pwm mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const int slew_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	 2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	  500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int xz3216_set_ramp(struct regulator_dev *rdev, int ramp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct xz3216 *xz3216 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	int regval = -1, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	for (i = 0; i < ARRAY_SIZE(slew_rates); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		if (ramp <= slew_rates[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			regval = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (regval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		dev_err(xz3216->dev, "unsupported ramp value %d\n", ramp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return regmap_update_bits(xz3216->regmap, XZ3216_CONTR_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				  CTL_SLEW_MASK, regval << CTL_SLEW_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct regulator_ops xz3216_dcdc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.get_mode = xz3216_dcdc_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.set_mode = xz3216_dcdc_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.set_suspend_voltage = xz3216_dcdc_set_sleep_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.set_suspend_enable = xz3216_dcdc_suspend_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.set_suspend_disable = xz3216_dcdc_suspend_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.set_suspend_mode = xz3216_dcdc_set_suspend_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.set_ramp_delay = xz3216_set_ramp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static struct regulator_desc regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.name = "XZ_DCDC1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.supply_name = "vin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		.id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		.ops = &xz3216_dcdc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.n_voltages = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		.enable_time = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		.enable_reg = XZ3216_BUCK1_SET_VOL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.enable_mask = VSEL_BUCK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.min_uV = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		.uV_step = 12500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		.vsel_reg = XZ3216_BUCK1_SET_VOL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.vsel_mask = VSEL_NSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const struct regmap_config xz3216_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct of_device_id xz3216_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	{ .compatible = "xz3216"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MODULE_DEVICE_TABLE(of, xz3216_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct of_regulator_match xz3216_reg_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	{ .name = "xz_dcdc1", .driver_data = (void *)0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static struct xz3216_board *xz3216_parse_dt(struct xz3216 *xz3216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct xz3216_board *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct device_node *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct device_node *xz3216_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	xz3216_np = of_node_get(xz3216->dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (!xz3216_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		DBG_ERR("could not find pmic sub-node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	regs = of_find_node_by_name(xz3216_np, "regulators");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	count = of_regulator_match(xz3216->dev, regs, xz3216_reg_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				   XZ3216_NUM_REGULATORS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	of_node_put(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	pdata = devm_kzalloc(xz3216->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	pdata->xz3216_init_data = xz3216_reg_matches[0].init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	pdata->of_node = xz3216_reg_matches[0].of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static struct xz3216_board *xz3216_parse_dt(struct i2c_client *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int xz3216_i2c_probe(struct i2c_client *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			    const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct xz3216 *xz3216;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	struct xz3216_board *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	DBG("%s, line=%d\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	xz3216 = devm_kzalloc(&i2c->dev, sizeof(struct xz3216),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 						GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if (!xz3216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	if (i2c->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		match = of_match_device(xz3216_of_match, &i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			DBG_ERR("Failed to find matching dt id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	xz3216->regmap = devm_regmap_init_i2c(i2c, &xz3216_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (IS_ERR(xz3216->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		dev_err(&i2c->dev, "Failed to allocate regmap!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		return PTR_ERR(xz3216->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	xz3216->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	xz3216->dev = &i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	i2c_set_clientdata(i2c, xz3216);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	pdev = dev_get_platdata(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		pdev = xz3216_parse_dt(xz3216);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		xz3216->num_regulators = XZ3216_NUM_REGULATORS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		xz3216->rdev = kcalloc(XZ3216_NUM_REGULATORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 					sizeof(struct regulator_dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 					GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		if (!xz3216->rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		/* Instantiate the regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		xz3216->regulator = pdev->xz3216_init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		if (xz3216->dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			config.of_node = pdev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		config.dev = xz3216->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		config.driver_data = xz3216;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		config.init_data = xz3216->regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		xz3216->rdev = devm_regulator_register(xz3216->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 						&regulators[0], &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		ret = PTR_ERR_OR_ZERO(xz3216->rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			dev_err(&i2c->dev, "Failed to register regulator!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int xz3216_i2c_remove(struct i2c_client *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	struct xz3216 *xz3216 = i2c_get_clientdata(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	if (xz3216->rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		regulator_unregister(xz3216->rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	i2c_set_clientdata(i2c, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct i2c_device_id xz3216_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	{ "xz3216", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MODULE_DEVICE_TABLE(i2c, xz3216_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct i2c_driver xz3216_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		.name = "xz3216",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		.of_match_table = of_match_ptr(xz3216_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	.probe = xz3216_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	.remove = xz3216_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	.id_table = xz3216_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int __init xz3216_module_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	ret = i2c_add_driver(&xz3216_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		pr_err("Failed to register I2C driver: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) subsys_initcall_sync(xz3216_module_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static void __exit xz3216_module_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	i2c_del_driver(&xz3216_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) module_exit(xz3216_module_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MODULE_AUTHOR("zhangqing <zhangqing@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MODULE_DESCRIPTION("xz3216 PMIC driver");