^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // wm831x-ldo.c -- LDO driver for the WM831x series
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright 2009 Wolfson Microelectronics PLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mfd/wm831x/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/wm831x/regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mfd/wm831x/pdata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define WM831X_LDO_MAX_NAME 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WM831X_LDO_CONTROL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WM831X_LDO_ON_CONTROL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define WM831X_LDO_SLEEP_CONTROL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WM831X_ALIVE_LDO_ON_CONTROL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WM831X_ALIVE_LDO_SLEEP_CONTROL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct wm831x_ldo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) char name[WM831X_LDO_MAX_NAME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) char supply_name[WM831X_LDO_MAX_NAME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct wm831x *wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct regulator_dev *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static irqreturn_t wm831x_ldo_uv_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct wm831x_ldo *ldo = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) regulator_notifier_call_chain(ldo->regulator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) REGULATOR_EVENT_UNDER_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * General purpose LDOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const struct linear_range wm831x_gp_ldo_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) REGULATOR_LINEAR_RANGE(900000, 0, 14, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) REGULATOR_LINEAR_RANGE(1700000, 15, 31, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int wm831x_gp_ldo_set_suspend_voltage(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct wm831x *wm831x = ldo->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int sel, reg = ldo->base + WM831X_LDO_SLEEP_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) sel = regulator_map_voltage_linear_range(rdev, uV, uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (sel < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return wm831x_set_bits(wm831x, reg, WM831X_LDO1_ON_VSEL_MASK, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static unsigned int wm831x_gp_ldo_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct wm831x *wm831x = ldo->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int ctrl_reg = ldo->base + WM831X_LDO_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int on_reg = ldo->base + WM831X_LDO_ON_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ret = wm831x_reg_read(wm831x, on_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (!(ret & WM831X_LDO1_ON_MODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = wm831x_reg_read(wm831x, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (ret & WM831X_LDO1_LP_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return REGULATOR_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return REGULATOR_MODE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int wm831x_gp_ldo_set_mode(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct wm831x *wm831x = ldo->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int ctrl_reg = ldo->base + WM831X_LDO_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int on_reg = ldo->base + WM831X_LDO_ON_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ret = wm831x_set_bits(wm831x, on_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) WM831X_LDO1_ON_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case REGULATOR_MODE_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret = wm831x_set_bits(wm831x, ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) WM831X_LDO1_LP_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = wm831x_set_bits(wm831x, on_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) WM831X_LDO1_ON_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) WM831X_LDO1_ON_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case REGULATOR_MODE_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ret = wm831x_set_bits(wm831x, ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) WM831X_LDO1_LP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) WM831X_LDO1_LP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ret = wm831x_set_bits(wm831x, on_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) WM831X_LDO1_ON_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) WM831X_LDO1_ON_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int wm831x_gp_ldo_get_status(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct wm831x *wm831x = ldo->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int mask = 1 << rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Is the regulator on? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ret = wm831x_reg_read(wm831x, WM831X_LDO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (!(ret & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return REGULATOR_STATUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Is it reporting under voltage? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = wm831x_reg_read(wm831x, WM831X_LDO_UV_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return REGULATOR_STATUS_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = wm831x_gp_ldo_get_mode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return regulator_mode_to_status(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static unsigned int wm831x_gp_ldo_get_optimum_mode(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int input_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int output_uV, int load_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (load_uA < 20000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return REGULATOR_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (load_uA < 50000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return REGULATOR_MODE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct regulator_ops wm831x_gp_ldo_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .set_suspend_voltage = wm831x_gp_ldo_set_suspend_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .get_mode = wm831x_gp_ldo_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .set_mode = wm831x_gp_ldo_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .get_status = wm831x_gp_ldo_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .get_optimum_mode = wm831x_gp_ldo_get_optimum_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .get_bypass = regulator_get_bypass_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .set_bypass = regulator_set_bypass_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int wm831x_gp_ldo_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct wm831x_pdata *pdata = dev_get_platdata(wm831x->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct wm831x_ldo *ldo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (pdata && pdata->wm831x_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) id = (pdata->wm831x_num * 10) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) id = pdev->id - id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_dbg(&pdev->dev, "Probing LDO%d\n", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ldo = devm_kzalloc(&pdev->dev, sizeof(struct wm831x_ldo), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!ldo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ldo->wm831x = wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) res = platform_get_resource(pdev, IORESOURCE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (res == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_err(&pdev->dev, "No REG resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ldo->base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) snprintf(ldo->name, sizeof(ldo->name), "LDO%d", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ldo->desc.name = ldo->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) snprintf(ldo->supply_name, sizeof(ldo->supply_name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "LDO%dVDD", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ldo->desc.supply_name = ldo->supply_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ldo->desc.id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ldo->desc.type = REGULATOR_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ldo->desc.n_voltages = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ldo->desc.ops = &wm831x_gp_ldo_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ldo->desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ldo->desc.vsel_reg = ldo->base + WM831X_LDO_ON_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ldo->desc.vsel_mask = WM831X_LDO1_ON_VSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ldo->desc.enable_reg = WM831X_LDO_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ldo->desc.enable_mask = 1 << id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ldo->desc.bypass_reg = ldo->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ldo->desc.bypass_mask = WM831X_LDO1_SWI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ldo->desc.linear_ranges = wm831x_gp_ldo_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ldo->desc.n_linear_ranges = ARRAY_SIZE(wm831x_gp_ldo_ranges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) config.dev = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) config.init_data = pdata->ldo[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) config.driver_data = ldo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) config.regmap = wm831x->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ldo->regulator = devm_regulator_register(&pdev->dev, &ldo->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (IS_ERR(ldo->regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ret = PTR_ERR(ldo->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_err(wm831x->dev, "Failed to register LDO%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) id + 1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) wm831x_ldo_uv_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) IRQF_TRIGGER_RISING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ldo->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ldo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) platform_set_drvdata(pdev, ldo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static struct platform_driver wm831x_gp_ldo_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .probe = wm831x_gp_ldo_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .name = "wm831x-ldo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * Analogue LDOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct linear_range wm831x_aldo_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) REGULATOR_LINEAR_RANGE(1000000, 0, 12, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) REGULATOR_LINEAR_RANGE(1700000, 13, 31, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int wm831x_aldo_set_suspend_voltage(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct wm831x *wm831x = ldo->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int sel, reg = ldo->base + WM831X_LDO_SLEEP_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) sel = regulator_map_voltage_linear_range(rdev, uV, uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (sel < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return wm831x_set_bits(wm831x, reg, WM831X_LDO7_ON_VSEL_MASK, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static unsigned int wm831x_aldo_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct wm831x *wm831x = ldo->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int on_reg = ldo->base + WM831X_LDO_ON_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret = wm831x_reg_read(wm831x, on_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (ret & WM831X_LDO7_ON_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return REGULATOR_MODE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int wm831x_aldo_set_mode(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct wm831x *wm831x = ldo->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int on_reg = ldo->base + WM831X_LDO_ON_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = wm831x_set_bits(wm831x, on_reg, WM831X_LDO7_ON_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) case REGULATOR_MODE_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = wm831x_set_bits(wm831x, on_reg, WM831X_LDO7_ON_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) WM831X_LDO7_ON_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int wm831x_aldo_get_status(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct wm831x *wm831x = ldo->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int mask = 1 << rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Is the regulator on? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ret = wm831x_reg_read(wm831x, WM831X_LDO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (!(ret & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return REGULATOR_STATUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Is it reporting under voltage? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = wm831x_reg_read(wm831x, WM831X_LDO_UV_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (ret & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return REGULATOR_STATUS_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = wm831x_aldo_get_mode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return regulator_mode_to_status(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const struct regulator_ops wm831x_aldo_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .set_suspend_voltage = wm831x_aldo_set_suspend_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .get_mode = wm831x_aldo_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .set_mode = wm831x_aldo_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .get_status = wm831x_aldo_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .set_bypass = regulator_set_bypass_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .get_bypass = regulator_get_bypass_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int wm831x_aldo_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct wm831x_pdata *pdata = dev_get_platdata(wm831x->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct wm831x_ldo *ldo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (pdata && pdata->wm831x_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) id = (pdata->wm831x_num * 10) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) id = pdev->id - id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_dbg(&pdev->dev, "Probing LDO%d\n", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ldo = devm_kzalloc(&pdev->dev, sizeof(struct wm831x_ldo), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (!ldo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ldo->wm831x = wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) res = platform_get_resource(pdev, IORESOURCE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (res == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_err(&pdev->dev, "No REG resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ldo->base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) snprintf(ldo->name, sizeof(ldo->name), "LDO%d", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ldo->desc.name = ldo->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) snprintf(ldo->supply_name, sizeof(ldo->supply_name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) "LDO%dVDD", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ldo->desc.supply_name = ldo->supply_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ldo->desc.id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ldo->desc.type = REGULATOR_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ldo->desc.n_voltages = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ldo->desc.linear_ranges = wm831x_aldo_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ldo->desc.n_linear_ranges = ARRAY_SIZE(wm831x_aldo_ranges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ldo->desc.ops = &wm831x_aldo_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ldo->desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ldo->desc.vsel_reg = ldo->base + WM831X_LDO_ON_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ldo->desc.vsel_mask = WM831X_LDO7_ON_VSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ldo->desc.enable_reg = WM831X_LDO_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ldo->desc.enable_mask = 1 << id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ldo->desc.bypass_reg = ldo->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ldo->desc.bypass_mask = WM831X_LDO7_SWI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) config.dev = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) config.init_data = pdata->ldo[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) config.driver_data = ldo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) config.regmap = wm831x->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ldo->regulator = devm_regulator_register(&pdev->dev, &ldo->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (IS_ERR(ldo->regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = PTR_ERR(ldo->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dev_err(wm831x->dev, "Failed to register LDO%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) id + 1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) wm831x_ldo_uv_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) IRQF_TRIGGER_RISING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ldo->name, ldo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) platform_set_drvdata(pdev, ldo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static struct platform_driver wm831x_aldo_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .probe = wm831x_aldo_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .name = "wm831x-aldo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * Alive LDO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define WM831X_ALIVE_LDO_MAX_SELECTOR 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static int wm831x_alive_ldo_set_suspend_voltage(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct wm831x *wm831x = ldo->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int sel, reg = ldo->base + WM831X_ALIVE_LDO_SLEEP_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) sel = regulator_map_voltage_linear(rdev, uV, uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (sel < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return wm831x_set_bits(wm831x, reg, WM831X_LDO11_ON_VSEL_MASK, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int wm831x_alive_ldo_get_status(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct wm831x *wm831x = ldo->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int mask = 1 << rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Is the regulator on? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ret = wm831x_reg_read(wm831x, WM831X_LDO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (ret & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return REGULATOR_STATUS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return REGULATOR_STATUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static const struct regulator_ops wm831x_alive_ldo_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .set_suspend_voltage = wm831x_alive_ldo_set_suspend_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .get_status = wm831x_alive_ldo_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int wm831x_alive_ldo_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct wm831x_pdata *pdata = dev_get_platdata(wm831x->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct wm831x_ldo *ldo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (pdata && pdata->wm831x_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) id = (pdata->wm831x_num * 10) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) id = pdev->id - id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) dev_dbg(&pdev->dev, "Probing LDO%d\n", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ldo = devm_kzalloc(&pdev->dev, sizeof(struct wm831x_ldo), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (!ldo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ldo->wm831x = wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) res = platform_get_resource(pdev, IORESOURCE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (res == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dev_err(&pdev->dev, "No REG resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ldo->base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) snprintf(ldo->name, sizeof(ldo->name), "LDO%d", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ldo->desc.name = ldo->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) snprintf(ldo->supply_name, sizeof(ldo->supply_name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) "LDO%dVDD", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ldo->desc.supply_name = ldo->supply_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ldo->desc.id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ldo->desc.type = REGULATOR_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ldo->desc.n_voltages = WM831X_ALIVE_LDO_MAX_SELECTOR + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ldo->desc.ops = &wm831x_alive_ldo_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ldo->desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ldo->desc.vsel_reg = ldo->base + WM831X_ALIVE_LDO_ON_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ldo->desc.vsel_mask = WM831X_LDO11_ON_VSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ldo->desc.enable_reg = WM831X_LDO_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ldo->desc.enable_mask = 1 << id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ldo->desc.min_uV = 800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ldo->desc.uV_step = 50000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ldo->desc.enable_time = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) config.dev = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) config.init_data = pdata->ldo[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) config.driver_data = ldo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) config.regmap = wm831x->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ldo->regulator = devm_regulator_register(&pdev->dev, &ldo->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (IS_ERR(ldo->regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ret = PTR_ERR(ldo->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dev_err(wm831x->dev, "Failed to register LDO%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) id + 1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) platform_set_drvdata(pdev, ldo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static struct platform_driver wm831x_alive_ldo_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .probe = wm831x_alive_ldo_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .name = "wm831x-alive-ldo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static struct platform_driver * const drivers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) &wm831x_gp_ldo_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) &wm831x_aldo_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) &wm831x_alive_ldo_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static int __init wm831x_ldo_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) subsys_initcall(wm831x_ldo_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static void __exit wm831x_ldo_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) module_exit(wm831x_ldo_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* Module information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) MODULE_DESCRIPTION("WM831x LDO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) MODULE_ALIAS("platform:wm831x-ldo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) MODULE_ALIAS("platform:wm831x-aldo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) MODULE_ALIAS("platform:wm831x-aliveldo");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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